[SI-LIST] Re: Reducing SSO noise in an FPGA

One may also want to choose an FPGA BGA with a low impedance 
power/ground structure. We have seen some FPGAs that have the ground 
pins mostly located near the BGA package periphery. There is not a lot 
that can be done on the board to reduce SSN on such a device.
Thanks,
Vinu

Salkow, Steven wrote:

>Some FPGA Ibis models allow modeling of SSN. SSN is high speed stuff and
>High Q low inductance capacitors near VIO Power pins will help mitigate
>noise. Each capacitor value has its own effective bandwith, hence a
>combination like 100pf, 1000 PF, .01UF, and 0.1UF, 1.0UF extend the noise
>supression of power planes. The smaller the capacitors capacitance the
>smaller its radius of effectivity. PCB Via fill and planarization allows
>power pins of a BGA to go directly to GNDS and Power Pins.
>
>Steven Salkow
>Lockheed Martin
>3200 Zanker Rd
>San Jose, CA 95134
>(408) 473-4058
>steven.salkow@xxxxxxxx
>Fax (408) 473-3044
>
>
>  
>
>>-----Original Message-----
>>From: Fabrizio Zanella [SMTP:fzanella@xxxxxxxxxxxx]
>>Sent: Wednesday, June 25, 2003 9:02 AM
>>To:   si-list@xxxxxxxxxxxxx
>>Subject:      [SI-LIST] Reducing SSO noise in an FPGA
>>
>>I would like to hear about experiences regarding methods of reducing
>>simultaneous switching noise in a large FPGA, BGA package.  Let's assume
>>a 128bit bus, with a signal frequency of 100MHz.
>>How effective is adding ground planes 2 mils from the VCC planes in
>>reducing SSN? If one uses BC, does every VCC pin in the FPGA require
>>decoupling? And should the caps be tied to the BGA pins with blind vias
>>so they can be placed directly under the BGA?  What are the optimal
>>values for the decoupling capacitors, 0.1uf, 0.22uF?
>>
>>Thanks very much and regards,
>>
>>
>>Fabrizio Zanella
>>Principal Hardware Design Engineer
>>Broadbus Technologies
>>fzanella@xxxxxxxxxxxx
>>=20
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