[SI-LIST] Re: Reducing SSO noise in an FPGA

One shouldn't make a blanket statement that a cap larger than a certain =
capacitance is too large for decoupling, you have to consider the =
inductance and the ESR. A low inductance package can push the self =
resonance out (proportional to 1/sqrt(LC)) and low ESR can give you good =
performance in the region of the self resonant frequency.

Paraphrasing Howard Johnson from his book "High Speed Digital Design":
Figure out the package size, which fixes the inductance,
then use the largest capacitance you can get into that package.

Read the book for the fine argument that Dr. Johnson makes... or maybe =
he'll chime in here.

One caveat is that if you really do need filtering at a specific =
frequency above the self resonance of local (say Y5V) decoupling caps =
you can use C0G/NP0 low ESR caps to filter those high frequencies. I =
find 2700pF C0G caps give me excellent decoupling for ECL and RF =
circuits.

---
mkp=20

-----Original Message-----
From: Zhangkun [mailto:zhang_kun@xxxxxxxxxx]
Sent: Wednesday, June 25, 2003 5:04 PM
To: fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA


Dear Zanella

I think 0.1uF and 0.22uF is too large for decoupling. When the frequency =
goes up to 100MHz, these two kind of caps will be of no use...

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