[SI-LIST] Re: Reducing SSO noise in an FPGA

All the more reason to make the PDS clean.

Jim Freeman

-----Original Message-----
From: Juergen Flamm [mailto:jflamm@xxxxxxxxxxx] 
Sent: Wednesday, June 25, 2003 12:40 PM
To: jmartinson@xxxxxxxxxxxxxxxxx; fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA


More food for thought:

It is one thing to get clean power to the package pins on a board.
But can the device vendors be trusted in having designed the power =
distribution inside the BGA package and onto the die appropriately?
I've personally had the pleasure in the recent past to work with clients =
on analyzing SSO noise using SPECCTRAQuest, where we discovered that the =
BGA package was the main contributor to SSO noise.=20

Best Regards

 Juergen Flamm
Senior Technical Leader         Office Phone: 1-818-881-9965 =20
PCB Systems Division            Cell Phone:     1-818-642-2633
Cadence Design Systems, Inc.    Help Desk:      1-877-237-4911
898 North Sepulveda Blvd, Suite 775     E-Mail:   jflamm@xxxxxxxxxxx
El Segundo, CA 90245    Web Site: http://www.cadencepcb.com

Register for one of our FREE upcoming seminars,=20
visit  http://www.cadencepcb.com/aboutus/events.asp

-----Original Message-----
From: Jerry Martinson [mailto:jmartinson@xxxxxxxxxxxxxxxxx]=20
Sent: Wednesday, June 25, 2003 11:51 AM
To: fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA

Fabrizio,

Here's my bag of tricks for getting the most for my money decoupling
BGAs. Some of these are commonly done but others aren't.  I think that
these techniques are effective, easy, and inexpensive but occasionally I
find that something I've been doing isn't always such a good idea.
Hopefully other people on the si-list who are knowledgeable can comment
on whether they think these techniques are a good ideas or not (and
maybe add a few tricks of their own).

The general #1 goal is to cut the inductance.

One trick I've used is to fill the signal layers with alternating power
and grounds directly underneath the power section of the BGA.  Some (Lee
Ritchey) even advocate doing this generally all over the board - which
is obviously better if you can do it.  Be careful when doing this so as
not to change the impedance of any impedance-sensitive nets on adjacent
layers in the area.  The local filling under the BGA power section often
works out very well for this particular case because there's not much
trace routing that gets done underneath the center of BGAs as it is hard
to get signals through there anyway.  Depending on your stackup, etc...
you'll get about 150 pF of extra plane capacitance doing this but more
importantly the "spreading inductance" of your power distribution will
be reduced in this area due to the parallel paths.  ** As a disclaimer I
have not thoroughly considered plane resonances with this approach **.
This resulting lowered spreading inductance will make the "effective
radius" of the nearby caps larger.=3D20

Obviously, the caps will be more effective if they are close to the part
but don't forget that it is perhaps even more important that they be on
the side of the board that is closest to the plane that you are
decoupling if the plane isn't near the center of the board (this is
another good argument to fill underneath the BGA).  There are some
formulas available on the web (Howard Johnson's SI site has a good
article on this) that can show the counter-intuitive sensitivity to the
side of the board the cap is on.  My experience is that many people
overlook this and put caps on the backside of the board so they can get
them "closer" because of the large topside keepout area required around
BGAs for the rework nozzle when the caps could have been better placed
on the topside of the board even though they would be further away.
Similarly, the power plane being closer to the targeted part helps as
well.

If your BGA is full matrix, you can fan the vias outward from the center
so you can get a "plus sign" of a handful of 0603 caps on the side of
the PCB directly underneath the BGA but this isn't a huge benefit if the
targeted power has a plane that is only near the top of the board.

If your PCB fab technology and fanout needs can tolerate high via
density, you can use a bunch of cap arrays instead of discretes.  The
solder joints look a little sloppy when assembled compared to the
resistor arrays but I haven't had real problems with them yet.  In
addition to regular cap arrays, AVX makes interdigitated cap arrays but
they are more expensive.  The benefit of the cap arrays is that you'll
probably have more vias (reducing inductance) than if you used a bunch
of 0603 or reverse-aspect caps.  What I like to do is to alternate power
and grounds just like you'd do if you used one of the AVX interdigitated
caps so some of the mag fields of the via pattern cancel out (how much
this helps I don't know).  Doing this also has the added benefit of
letting you switch to the better AVX IDC parts if you run into troubles.
I've always thought that a great product would be a cap array that can
fanout on a 1mm grid so it affects your trace escapes from your BGA less
but I haven't found one on the market yet.

Another problem is how do you even measure the power noise at the BGA
and not at the plane?  One thought I've had but haven't tried is to have
a few extra "test vias" or traces inside the power section of the BGA
that attaches to one of the power balls on the BGA (which still has a
regular via) but doesn't attach to the power planes.

As far as cap value selection, I'm not going to go there as so much has
been written about it what it does to resonance.  This is not that it's
not important but I'm not sure I'm the best at commenting on it.  BC is
absolutely a good thing but the special 2 mill dielectrics costs more
money.

As far as the FPGA is concerned, many modern FPGAs let you control the
IO's dI/dt by changing strength, slew, or source termination.  You may
also be able to stagger the switching a little bit so they don't all
switch at the same time.  If you can reduce the dI/dt without
compromising your design, you'll be reducing the problem at the source.


-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]=3D20
Sent: Wednesday, June 25, 2003 9:02 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Reducing SSO noise in an FPGA

I would like to hear about experiences regarding methods of reducing
simultaneous switching noise in a large FPGA, BGA package.  Let's assume
a 128bit bus, with a signal frequency of 100MHz.
How effective is adding ground planes 2 mils from the VCC planes in
reducing SSN? If one uses BC, does every VCC pin in the FPGA require
decoupling? And should the caps be tied to the BGA pins with blind vias
so they can be placed directly under the BGA?  What are the optimal
values for the decoupling capacitors, 0.1uf, 0.22uF?

Thanks very much and regards,


Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
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