[SI-LIST] Reducing SSO noise in an FPGA
- From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 25 Jun 2003 12:01:31 -0400
I would like to hear about experiences regarding methods of reducing
simultaneous switching noise in a large FPGA, BGA package. Let's assume
a 128bit bus, with a signal frequency of 100MHz.
How effective is adding ground planes 2 mils from the VCC planes in
reducing SSN? If one uses BC, does every VCC pin in the FPGA require
decoupling? And should the caps be tied to the BGA pins with blind vias
so they can be placed directly under the BGA? What are the optimal
values for the decoupling capacitors, 0.1uf, 0.22uF?
Thanks very much and regards,
Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
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