[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: Perry Qu <perry.qu@xxxxxxxxxxx>
- To: zhang_kun@xxxxxxxxxx
- Date: Thu, 26 Jun 2003 09:23:45 -0400
Hi, Zhangkun:
We have been using 100nF cap extensively in our high speed design (> 100MHz)
and so far so good. In my understanding, small ESL is the key to make a flat
impedance curve in frequency
range, as explained here many times by Larry Smith and Istvan Novak. Small caps
such as NPO 1nF will normally give us high Q since resonance factor increase
when ESL increase, and when
ESR and C decrease. For NPO cap, it has very small ESR and small C, so if we do
not control ESL to very small value, we will end up with high Q. Such high Q
cap may cause strong
anti-resonance when mixed with other cap and/or plane pairs. In our designs,
since we can't control ESL very well with special stackup/routing, we use 1nF
very carefully.
Regards
Perry
Zhangkun wrote:
> Dear Zanella
>
> I think 0.1uF and 0.22uF is too large for decoupling. When the frequency goes
> up to 100MHz, these two kind of caps will be of no use. Istvan has writen one
> paper about measuring caps.
>
> Best Regards
>
> Zhangkun
> 2003.06.26
> ----- Original Message -----
> From: "Fabrizio Zanella" <fzanella@xxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Thursday, June 26, 2003 12:01 AM
> Subject: [SI-LIST] Reducing SSO noise in an FPGA
>
> > I would like to hear about experiences regarding methods of reducing
> > simultaneous switching noise in a large FPGA, BGA package. Let's assume
> > a 128bit bus, with a signal frequency of 100MHz.
> > How effective is adding ground planes 2 mils from the VCC planes in
> > reducing SSN? If one uses BC, does every VCC pin in the FPGA require
> > decoupling? And should the caps be tied to the BGA pins with blind vias
> > so they can be placed directly under the BGA? What are the optimal
> > values for the decoupling capacitors, 0.1uf, 0.22uF?
> >
> > Thanks very much and regards,
> >
> >
> > Fabrizio Zanella
> > Principal Hardware Design Engineer
> > Broadbus Technologies
> > fzanella@xxxxxxxxxxxx
> > =20
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--
Perry Qu
Design & Qualification | 600 March Road
Alcatel Canada | Ottawa, ON K2K 2E6, Canada
DID: (613) 7846720 | FAX: (613) 5993642
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