[SI-LIST] Damped voltage oscillation

From: <ueda@xxxxxxxxxxxx>
To: "silists" <si-list@xxxxxxxxxxxxx>
Date: Sun, 22 Jun 2003 05:39:46 +0900

Hi, ALL
Does anyone know the example which damped voltage oscillation?
The resistor is connected with the series in decoupling capacitor to insert
between power(vdd) and ground (gnd).
Don't you know the paper, the materials?
Chihiro Ueda
AET japan INC


*************************
Engineering Division
Chihiro Ueda
AET JAPAN, INC.
URSIS Bldg. 9th Floor
1-2-3 Manpukuji, Asaoku,
Kawasaki-City,215-0004Japan
TEL:81-044-966-9981
FAX:81-044-951-1572
mailto:ueda@xxxxxxxxxxxx
http://www.aetjapan.com
*************************


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[SI-LIST] Re: Damped voltage oscillation
From: istvan novak

[SI-LIST] Re: Damped voltage oscillation
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[SI-LIST] Damped voltage oscillation

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