[SI-LIST] Re: Reducing SSO noise in an FPGA _ Capacitor ESL-values
- From: "Bart Bouma" <bart.bouma@xxxxxxxxx>
- To: steven.salkow@xxxxxxxx
- Date: Thu, 26 Jun 2003 12:06:14 +0200
Hi,
mentioned ESL values for the 0805 and 0508 capacitors appear a bit high to
me (IMHO). A matter of measurement method, I think. For equally sized caps
should show more or less equal ESL-values (the geometry of the part mainly
determines the part's inductance, i.e. lenght, width and height). But,
unfortunately published ESL values for capacitors vary largely from
manufacturer to manufacturer (e.g. I noticed a difference of a factor 3
(three!) between the published ESL values for a 0508 low inductance
capacitor). Listed below are the ESL-values we have measured
Used measurement setup:
Fixture HP16192A; fixture short compensation done by contacting the
electrodes directly (no dummy used, which would introduce an additional
variable to take in account). LCR meter Agilent 4287A and/or Impedance
Analyzer HP4291.
Our measurements gave following typical ESL values (on our Phycomp parts):
1210 : 1.0nH (same lenght as 1206, but wider, which results in a lower
ESL-value)
1206 : 1.2nH
0612 : 0.4nH
0805 : 0.9nH
0508 : 0.3nH
Clearly the wider and reversed geometry (RG) parts are in favor w.r.t.
ESL.
Even better are the "new" 0306 parts: compared to a 0603 sized capacitor:
0603 : 0.7nH
0306 : 0.2nH
? The next step for RG capacitors => 0204 (ESL ~ 0.15nH ?) or even 0102
(ESL ~ 0.10nH ?) ??
to be complete, ESL values for our smallest parts:
0402 : 0.52nH (fixture 16196B)
0201 : 0.40nH (fixture 16196C)
Finally I like to mention the ESL-value of one of our X2Y capacitors
(measured with VNA and capacitor mounted on a small 1mm thick FR-4 board):
example; a 1812 sized X2Y, ESL calculated from impedance @ 1 GHz => 700
milliOhm => ESL aprox. 110pH (ESR contribution neglected).
Compare this value to the ESL-value of a standard 1812 MLCC, this will be
about 1.5 - 2nH (not measured).
BTW: this X2Y shows an impedance of 70 milliOhm at 100 MHz. Low enough?
Hopefully my small contribution will bring some clarity in the world of
low inductance capacitors.
As seen in another thread on the SI-list (Specctraquest model - mounted
inductance) it is neccesary to standardize the ESL/inductance measurements
on decoupling capacitors (standardized fixtures/boards), and possibly
close to the situation in what it will be applied.
Are there some other capacitor manufacturers on the list who are willing
to contribute to this discussion?
kind regards, Bart Bouma
MLCC appl. eng.
phycomp - the Netherlands
www.yageo.com
================================================================================
Mr Zhangkun is quite right to suggest that for 100 Mhz no practical =
parts
are known to exist for 0.1uF and 0.22uF that have an effective =
impedance at
100 Mhz. Michael Poimboeuf is right to suggest that low inductance low =
ESR
parts make a difference. Here are a few vendors that have some better =
parts
(higher Q)
For practical parts look at=20
JDI Low Inductance Capacitors at http://www.johansondielectrics.com
AVX http://www.avxcorp.com/docs/masterpubs/lica.pdf
and Syfer Technology http://www.syfer.com/5115.htm
The last vendor states" Correspondingly, an inductance of 1200pH for =
0805
(capacitor) is reduced to around 600pH for the 0508. "
AVX has what they refer to as a LICA=AE (Low Inductance Decoupling =
Capacitor
Arrays)
Small Ceramic capacitor now available up to 15 UF now have better
performance at lower frequencies that previous units.
Steven Salkow
Lockheed Martin
3200 Zanker Rd
San Jose, CA 95134
(408) 473-4058
steven.salkow@xxxxxxxx
Fax (408) 473-3044
> -----Original Message-----
> From: Michael Poimboeuf [SMTP:Michael_Poimboeuf@xxxxxxxxxxxxxx]
> Sent: Wednesday, June 25, 2003 5:27 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>=20
> One shouldn't make a blanket statement that a cap larger than a =
certain =3D
> capacitance is too large for decoupling, you have to consider the =3D
> inductance and the ESR. A low inductance package can push the self =
=3D
> resonance out (proportional to 1/sqrt(LC)) and low ESR can give you =
good =3D
> performance in the region of the self resonant frequency.
>=20
> Paraphrasing Howard Johnson from his book "High Speed Digital =
Design":
> Figure out the package size, which fixes the inductance,
> then use the largest capacitance you can get into that package.
>=20
> Read the book for the fine argument that Dr. Johnson makes... or =
maybe =3D
> he'll chime in here.
>=20
> One caveat is that if you really do need filtering at a specific =3D
> frequency above the self resonance of local (say Y5V) decoupling caps =
=3D
> you can use C0G/NP0 low ESR caps to filter those high frequencies. I =
=3D
> find 2700pF C0G caps give me excellent decoupling for ECL and RF =3D
> circuits.
>=20
> ---
> mkp=3D20
>=20
> -----Original Message-----
> From: Zhangkun [mailto:zhang_kun@xxxxxxxxxx]
> Sent: Wednesday, June 25, 2003 5:04 PM
> To: fzanella@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>=20
>=20
> Dear Zanella
>=20
> I think 0.1uF and 0.22uF is too large for decoupling. When the =
frequency =3D
> goes up to 100MHz, these two kind of caps will be of no use...
>=20
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