[SI-LIST] Re: resend - Specctraquest model: mounted inductance
- From: "Bart Bouma" <bart.bouma@xxxxxxxxx>
- To: Larry Smith <Larry.Smith@xxxxxxx>
- Date: Thu, 5 Jun 2003 16:13:34 +0200
Larry,
thanks for your very detailed answer. I like the Transfer Impedance
approach.
You are right when mentioning that the pcb will have 4 vias (Vdd1, Vdd2
and 2 gnd vias)
I will concentrate on the X2Y: it's the most interesting three (or 4 )
terminal capacitor.
I'm afraid that your idea on how the model of the X2Y looks like is more
or less based on the feeedthrough capacitor.
The X2Y is not a feedthrough capacitor, e.g. it has no DC-connection between
the the "terminations" Vdd1 and
Vdd2.
It should be used as a bypass or shunt component, providing a low
impedance path to ground over a broad frequency range.
Compare this to what you wrote:
"If on the other hand, we obtained -120 dB "transfer impedance" by
keeping the series L and R small and by having a very low
capacitive impedance (high capacitance), we have a DUT that may be able
to conduct the 100 amps from vdd1 to vdd2".
The good insertion loss figures that the X2Y shows are not because it has
large LLL's, but because of a very low impedance of the capacitor to
ground, and the X2Y is very well capable of passing by large currents. The
X2Y doesn't carry DC-current.
The X2Y described simply: the X2Y capacitor consists of 2 capacitors in
one package. These two caps can be assumed as connected in series, and
have a common centre node (the 2 ground connections) formed by two
side-terminations (so from the outside, it looks like a feedthru, but it
behaves quite differently).
This is the key to the X2Y's low inductance: currents flow in opposite
directions and magnetic fields cancel.
This has been shown with careful placement of 2 standard capacitors in a
paper by University of Missouri-Rolla and even in a patent by Dell.
The X2Y is in fact the same, but optimized and integrating the 2 caps in
one shielded package.
A third capacitor is formed by the 2 above mentioned capacitors in series.
This results in 2 line to ground capacitors (2 Y-caps) and 1 line to line
capacitor (1 X-cap).
In other terms: 1 cap between Vdd1 and Vdd2, and 2 caps placed between
Vdd1 & Gnd1, and Vdd2 & Gnd2.
vdd1 o
L
R
---
gnd1---------gnd2
.-.
L
R
vdd2 o
To be complete: here is a link to a paper that shows the internal
structure and the X2Y model:
http://www.x2y.com/cube/x2y.nsf/(files)/InternalModel060303.pdf/$FILE/InternalModel060303.pdf
We have been carrying out S21 Insertion Loss measurements on a small pcb,
this 2-sided pcb had one large ground plane at the bottom, the top-side
consists of a 50 Ohm microstrip line, with two smaller ground planes at
each side of it. Multiple vias conected the top-ground planes with the
bottom ground plane.
The pcb was mounted in a Wiltron Universal fixture, and the X2Y soldered
on the 50 Ohm microstrip line and grounded at the ground planes.
See for a more detailed document on this the link below.
Port 1 and port 2 connected to the same ground plane and to the same 50
Ohm line, but not at the same position.
Parallel to this the X2Y, which is located between the 50 Ohm line and
ground.
The X2Y was measured in 2 modes: 1 Y-cap only (your Vdd1 and Gnd1
terminals open) and both Y-caps connected.
You wrote:
" If you want to obtain a model for the capacitor to be used in SQPI
simulation, you would have to make a "transfer impedance" measurement by
connecting both port 1 and port 2 of the VNA to the vdd2
and gnd2 terminals of the DUT and leave the vdd1 and gnd1 terminals open. "
I think that what I described is comparable to your "transfer Impedance"
measurement. Do you agree?.
See also the link below.
? But how to differentiate the intrinsic inductance from the mounting
inductance ?
Re. to S11 and S22: when a well defined fixture is used, I believe that
these two parameters can be measured quite well upto high frequencies.
Condition: a well done calibration.
But I am aware that by the limitations of the Vector Network Analyzer low
impedances, or high impedances (i.e. far away from the 50Ohm of the
system), can't be measured in this way. I think the limit lies at aprox
100 milliOhm or at -48dB.
Larry, one last issue: you mentioned folowing:
" This measurement will be far different than the "insertion loss"
measurements given by the 3 terminal cap manufactures. One measurement
has to do with power going "through" a component, the other measurement
has to do with power getting "past" a component on highly conductive
power planes."
The "through" measurement refer to feedthrough capacitors, I assume.
But is this "past" measurement not identical to your transfer measurement?
When using higly conductive power planes, one can assume that both ports
are connected to the same power planes.
Or do I overlook something?
I think I do understand your S21 measurement and how you extract the Z21
transfer impedance from the S21 data.
I think that the measurement method I described, i.e. the X2Y on a small
pcb, is identical to your transfer measurement.
What do you think?
We don't carry out the S21 to Z21 conversion. Just showing the S21
Insertion Loss data.
Here a link to measurements we did on the X2Y mounted on this pcb: it
shows clearly the better performance of the X2Y over standard MLCCs.
The X2Y performs at least 10dB better - at frequencies beyond its
resonance frequency - than 2 standard MLCCs connected in parallel.
http://www.x2y.com/cube/x2y.nsf/(files)/X2YMLCC.pdf/$FILE/X2YMLCC.pdf
Thanks again,
kind regards,
Bart Bouma
appl. eng.
www.yageo.com
=============================================================================
Bart - To directly answer your question about mounting inductance, I
believe you will want to treat the mount as if the capacitor is a 4
terminal device. As I understand it, the PCB will have 4 vias with the
two end vias going to vdd1 and vdd2 and the two middle vias going to gnd
on a PCB that has a stackup something like this:
pads
vdd2
gnd
vdd1
more layers...
Since there are 4 vias and 4 pads, an inductance matrix involving 4
conductors will handle the situation. An EM solver can be used to find
the inductance matrix. Measurement of this matrix will be difficult.
This brings up some questions about how many terminals the "3 terminal
capacitor" has? What is the topology of the circuit model that will be
simulated? Several years ago, I asked similar questions to the
manufactures of the X2Y capacitor but did not get any clear answers.
They basically told me not to worry about what is inside the caps and
just look at the measurements. That is when I got really worried...
To go any further in this discussion, we need to clearly define some
terminology. For this discussion, I would like to distinguish between
"insertion loss" and "transfer impedance". People use both of these
terms when referring to an S21 measurement but I would interpret these
very differently, even though the magnitude and phase may be
identical. First, we need a circuit topology.
I don't know what is inside of an X2Y package, but I will speculate
with the following circuit diagram (hope this works out...):
vdd1 o--LLL-----LLL-----LLL-----LLL-----LLL-----o vdd2
| | | |
--- --- --- ---
.-. .-. .-. .-.
| | | |
gnd1 o--LLL-----LLL-----LLL-----LLL-----LLL-----o gnd2
Please consider each inductor (LLL) to also have a resistance. I
believe that if you attached an ohm meter to the vdd1 and vdd2
terminals, current would flow through the part with some resistance.
The gnd1 and gnd2 terminals would behave the same way. You would
measure a capacitance between either of the vdd and gnd terminals.
(Somebody please correct me if I am wrong about this..) The above
diagram behaves in this way. Let's say that the VRM (power source) is
attached to vdd1 and the load (power sink) is attached to vdd2. Gnd1
and Gnd2 will end up being attached to the single gnd plane through two
inductive vias. Vdd1 and Vdd2 are connected to different power planes
through two more vias, 4 inductive connections in all.
Now, back to "insertion loss" and "transfer impedance". You might make
a full 2 port measurement of this device by connecting port 1 of a VNA
to vdd1 and gnd1; and connect port 2 to vdd2 and gnd2. Gnd1 and gnd2
may even be shorted together if the measurement is made with the DUT
mounted on a PCB. The S21 measurement will tell us how much of the
wave from port 1 made it to port 2. If this is a good DUT, we will
probably see something like -60dB for S21 in some frequency range.
This is the traditional meaning of insertion loss. Not much of the
signal got through. Note that we could get large insertion loss by two
different means: we could make the L and R series impedance very large,
or we could make the capacitive admittance very large (capacitive
impedance very small).
In fact, we could make the LLL's high inductance (and high resistance,
nearly an open circuit) so that there was little conductivity from vdd1
to vdd2 and have extreme insertion loss, perhaps -120 dB. But should
this be interpreted as a low impedance power distribution system (PDS)
that is capable of bringing 100 amps from vdd1 to vdd2? Absolutely not.
If on the other hand, we obtained -120 dB "transfer impedance" by
keeping keeping the series L and R small and by having a very low
capacitive impedance (high capacitance), we have a DUT that may be able
to conduct the 100 amps from vdd1 to vdd2. From the S21 measurement,
you cannot tell what you have. If you could make clean S11 and S22
measurements on the DUT, you could figure out how the DUT will perform
in a PDS. But S11 and S22 measurements below about 60 dB and above 10
MHz are very inaccurate because the inductance of the fixture dominates
and it is very difficult to to calibrate or compensate it out. Yet this
is the frequency and impedance range where power distribution is
very important.
Therefor, the engineers at Sun Microsystems have been using the phrase
"transfer impedance" when we refer to the S21 measurement that involves
port 1 and port 2 of the VNA connected to the same conductors. A good
example of this is when we take power plane measurements with port 1
and port 2 each connected to vdd and gnd of the same power planes, but
at different locations. An ohm meter would tell you that port 1 and
port 2 are connected in parallel, but at high frequency, this is not
the case. Istvan Novak has discussed a good way to obtain the "self
impedance" (S11 at one point on the power planes) by probing the same
Vdd and Ground vias with port 1 on top and port 2 on the bottom of the
PCB. The probe inductance does not hurt you in this "transfer
impedance" measurement. It is a lot like 4 port kelvin probes for DC
measurements.
In a similar way, I often solder port 1 and port 2 of the VNA to a two
terminal decoupling capacitor to obtain the impedance vs frequency.
With PDS and capacitor measurements made in this way, it is possible to
obtain accurate S21 readings of -80 dB at more than 100 MHz (transfer
impedance), which is far beyond the published accuracy of the
instrumentation. But, this should not be interpreted as insertion
loss, if you understand my distinction between the two terms. Istvan
has published several papers at Design Conn on the measurment of low
impedances at high frequencies. We really want to know the S11
(actually the Z11) for the PDS but that is too difficult to measure, so
we measure S21, convert it to Z21 and call it a transfer impedance.
Subtle, but important.
Now, back to the 3 terminal capacitor... Be very careful about
interpreting the insertion loss measured on a 3 terminal capacitor as
being the low impedance presented to a power distribution system. It
is not. If you want to obtain a model for the capacitor to be used in
SQPI simulation, you would have to make a "transfer impedance"
measurement by connecting both port 1 and port 2 of the VNA to the vdd2
and gnd2 terminals of the DUT and leave the vdd1 and gnd1 terminals
open. This measurement will be far different than the "insertion loss"
measurements given by the 3 terminal cap manufactures. One measurement
has to do with power going "through" a component, the other measurement
has to do with power getting "past" a component on highly conductive
power planes.
Essentially, the 3 terminal capacitor isolates the vdd1 node from noise
on the vdd2 node, and vice versa. This may be very useful for
providing clean power to analog circuits such as a PLL. But we have to
be very careful in the interpretation of the S21 measurements for PDS
components. This discussion is closely related to the discussion that
we had on ports and terminals several weeks ago under subject thread
"N-port model limitations in simulators"
regards,
Larry Smith
Sun Microsystems
> Larry,
> Thanks for your answer.
> Yes, we are looking for mounting inductance of a decoupling capacitor
for
> use in the SQPI tool.
> As you know, models for this require inductance values for the part
itself
> (intrinsic inductance) and inductance associated with mounting.
> You wrote: " .. measure the loop inductance on an existing product or
test
board ...", I agree, this can be done quite well on a two terminal device
> (standard MLCC).
> But how to measure this for a three terminal device, like an feedthru or
a
> X2Y-capacitor?
> Especially the latter: the X2Y consists of 3 embedded capacitors and
forms
> actually 3 current loops.
>
> Following describes how we think how to attach a three-terminal device,
> like the X2Y.
> The ideal situation would be that both end-terminations - as a standard
> two terminal capacitor has - are attached to two powerplanes, e.g. as
you
> mentioned Vdd and Vdd2. The third terminal, which actually consists of
two
> side connections (internally connected to each other) must be connected
to
> a ground plane in between with at least 2 via's. One at each side of the
> part..
> Stackup: Vdd - Gnd - Vdd2 with equal distances between the planes.
>
> There will be a power flow through the feedthru capacitor, which will
> result in some power loss due to its series resistance.
> But not in case of the X2Y, which is attached in bypass (shunt).
> In case of the X2Y, measurements have shown that a very low impedance
over
> a broad frequency range can be reached, due too its low intrinsic ESL,
and
> low ESR (as presented at CARTS2002 USA & Europe).
> The intrinsic inductance of the part itself can be extracted very well
by
> a VNA 2-port measurement (as described in some SUN-papers).
> The part is mounted in a low inductance fixture, designed for
> three-terminal devices and is de-embedded by a TRL-calibration.
>
> Now back to the mounting inductance:
> almost needless to mention, but to fully employ the low inductance
> character of e.g. the X2Y, mounting should be paid attention too.
> How to measure/determine/extract/estimate the mounting inductance for
> these three terminal devices.
> Can I assume the mounting inductance to be half the value of a standard
> capacitor with the same size?
> For from mounting point of view the two halves of e.g. the X2Y are
> paralleled. Or is this too simple?
> Do you have any additional suggestion?
>
> best regards,
> Bart Bouma
> www.yageo.com
>
>
>
> Bart - Are you looking for the mounting inductance associated with a
> decoupling capacitor to be used in the Spectra Quest Power Integrity
> tool? SQPI has a fast henry type of EM solver that will estimate the
> loop inductance for the Vdd/Gnd terminals. Or, you can do as we do and
> measure the loop inductance on an existing product or test board and
> insert the inductance manually.
>
> I must confess, I don't really know what to do with 3 terminal
> capacitors for the decoupling application. Where do you attach the 3
> terminals? Two of the terminals will be Vdd and Gnd, but where does
> the third terminal attach to the system? The mounting inductance
> for your 3 terminal device will be highly dependent on where the
> current is flowing (current and return current).
>
> Does power flow through the 3 terminal device? For example, do you
> hook it to Vdd, Gnd and Vdd2? Is Vdd2 a separate power plane in the
> PCB stackup? A 3 terminal capacitor used in this way may be very
> useful for a sensitive PLL or similar low power application. But the
> power consumer will be downstream of the relatively high series
> impedance of the 3 terminal device. It may be possible to meet a
> target impedance of several ohms using the 3 terminal device, but it
> will be very difficult to build a 1 mOhm power distribution system
> up to the 100 MHz range using 3 terminal capacitors.
>
> regards,
> Larry Smith
> Sun Microsystems
>
> >
> > Hi all,
> > I'm resending this post on Specctraquest mounted inductance. Until now
> no
> > reactions received on this topic.
> > Is there no one on the si-list who can help a vendor to generate
> > Specctraquest models?
> > I read so often that models are not available from vendors, now is
your
> > chance!
> > But I need some help. Please!
> >
> > Bart
> > www.yageo.com
> > ================ original post
========================================
> >
> > Hi all,
> >
> > I am starting to develop Specctraquest models for three-terminal
> > capacitors, e.g. a feedthru capacitor.
> > Does anybody know how to extract, or how to determine, the mounted
> > inductance of such a three-terminal capacitor?
> > Maybe someone already did this?
> >
> > For a two terminal device the loop-inductance can be determined quite
> > easily, but for a three terminal capacitor I could not find a single
> > reference.
> > Of course it all depends on substrate thickness, vias and layout, but
is
>
> > there a general method how to calculate the mounted inductance or
> > loop-inductance for such a device?
> > Any information is welcome!
> >
> > regards,
> > Bart Bouma
> > www.yageo.com
> >
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