Posts for si-list, 05-2003

Browse: Last Month: 04-2003 Main Archive Page Next Month: 06-2003

» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: Crystal Oscillator Overtones. -
» [SI-LIST] Re: RF cable standards -
» [SI-LIST] -
» [SI-LIST] Re: Crystal Oscillator Overtones. -
» [SI-LIST] Crystal Oscillator Overtones. -
» [SI-LIST] Re: si-list: Michael_Poimboeuf@digidesign.com post needs approval -
» [SI-LIST] Re: Ground problems -
» RE: [SI-LIST] Re: Ground problems -
» [SI-LIST] si-list: Michael_Poimboeuf@digidesign.com post needs approval -
» [SI-LIST] Re: Ground problems -
» [SI-LIST] Re: Ground problems -
» [SI-LIST] Re: Ground problems -
» [SI-LIST] Re: Ground problems -
» [SI-LIST] Re: Ground problems -
» [SI-LIST] RF cable standards -
» [SI-LIST] Signal Integrity Simulation Manager Needed -
» [SI-LIST] Re: Jitter measurement -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: Jitter measurement -
» [SI-LIST] Jitter measurement -
» [SI-LIST] Re: Decoupling capacitor placement -
» [SI-LIST] Re: Decoupling capacitor placement -
» [SI-LIST] Re: Decoupling capacitor placement -
» [SI-LIST] Kspice to Hspice -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: PCI Bus Routing -
» [SI-LIST] Re: Plated Contacts -
» [SI-LIST] Plated Contacts -
» [SI-LIST] Decoupling capacitor placement -
» [SI-LIST] PCI Bus Routing -
» [SI-LIST] Re: JTAG Interface -
» [SI-LIST] Agenda, IBIS Open Forum Summit at DAC -
» [SI-LIST] Specctraquest model: mounted inductance -
» [SI-LIST] Re: Ground problems -
» [SI-LIST] JTAG Interface -
» [SI-LIST] Re: Pull-up / pull-down R -
» [SI-LIST] Call for Participation Issued for 2004 IPC Printed Circuits Expo/APEX Joint Technical Conference -
» [SI-LIST] Pull-up / pull-down R -
» [SI-LIST] Re: Crosstalk FastHenry - ( Hspice Inverter Modeling ) -
» [SI-LIST] Re: transistor level SPICE models -
» [SI-LIST] RMCEMC SI/EMC Presentation slides available for download -
» [SI-LIST] transistor level SPICE models -
» [SI-LIST] Ground Problems -
» [SI-LIST] Ground problems -
» (no subject) -
» [SI-LIST] Re: Power supply inductors and EMI beads -
» [SI-LIST] generating PRBS -
» [SI-LIST] Re: Resonance Frequency -
» [SI-LIST] Re: looking for HP probe adapters -
» [SI-LIST] Re: Crosstalk FastHenry -
» [SI-LIST] Resonance Frequency -
» [SI-LIST] Re: Material on SI in ASIC -
» [SI-LIST] Re: looking for HP probe adapters -
» [SI-LIST] Re: looking for HP probe adapters -
» [SI-LIST] looking for HP probe adapters -
» [SI-LIST] Mixed signal: partitioning GND or unique plane ? -
» [SI-LIST] Re: HSTL standard question, -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] A question on PSpice Optimizer -
» [SI-LIST] Re: Power supply inductors and EMI beads -
» [SI-LIST] Power supply inductors and EMI beads -
» [SI-LIST] Re: Radiation masking noise measurements -
» [SI-LIST] Re: FW: The standard eye mask test -
» [SI-LIST] HSTL standard question, -
» [SI-LIST] FW: The standard eye mask test -
» [SI-LIST] CML vs. LVPECL -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Radiation masking noise measurements -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] [Fwd: Re: Re: Adding trace length for timing adjustment] -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] Impulse response of MMF -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Re: Negative Resistance of Crystal Oscillators -
» [SI-LIST] S parameters for complex designs -
» [SI-LIST] Re: Standard for thermal relief on thru hole pins -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] Negative Resistance of Crystal Oscillators -
» [SI-LIST] Re: Opening -
» [SI-LIST] Re: looking for IBIS model -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Re: Power plane noise measurement -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Re: Standard for thermal relief on thru hole pins -
» [SI-LIST] Power plane noise measurement -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Re: Standard for thermal relief on thru hole pins -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Opening -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Standard for thermal relief on thru hole pins -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] Job Opening -
» [SI-LIST] Re: Interconnect Simulations-V2 -
» [SI-LIST] looking for IBIS model -
» [SI-LIST] Re: Hspice question -
» [SI-LIST] Re: Hspice question -
» [SI-LIST] Interconnect Simulations-V2 -
» [SI-LIST] Re: [OT] Extreme vibration electronics -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Re: inductance extraction -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Interconnect Simulations -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Inductance extraction -
» [SI-LIST] inductance extraction -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Re: J.L. Prince (Influcence of a floating plane......) Arizona university -
» [SI-LIST] Re: J.L. Prince (Influcence of a floating plane......) Arizonauniversity -
» [SI-LIST] Re: J.L. Prince (Influcence of a floating plane......) Arizona university -
» [SI-LIST] Re: Hspice question -
» [SI-LIST] Re: Hspice question -
» [SI-LIST] Re: Hspice question -
» [SI-LIST] Re: Hspice question -
» [SI-LIST] Hspice question -
» [SI-LIST] look for books for specctra autorouting tool -
» [SI-LIST] Re: Adding trace length for timing adjustment -
» [SI-LIST] Re: Stripline, Microstrip Signal Attenuation -
» [SI-LIST] Re: SDRAM data issues -
» [SI-LIST] Re: Looking for Fast Ethernet IBIS File -
» [SI-LIST] The standard eye mask test -
» [SI-LIST] The standard eye mask test -
» [SI-LIST] Re: SDRAM data issues -
» [SI-LIST] Re: look for books -
» [SI-LIST] Re: SPECCTRAQuest crosstalk question -
» [SI-LIST] Re: Looking for Fast Ethernet IBIS File -
» [SI-LIST] Re: Looking for Fast Ethernet IBIS File -
» [SI-LIST] Dielectrics at "high" frequencies. -
» [SI-LIST] Re: Looking for Fast Ethernet IBIS File -
» [SI-LIST] Re: SDRAM data issues -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - 5/20 meeting announcement -
» [SI-LIST] Stripline, Microstrip Signal Attenuation -
» [SI-LIST] Re: look for books -
» [SI-LIST] Adding trace length for timing adjustment -
» [SI-LIST] Re: Looking for Fast Ethernet IBIS File -
» [SI-LIST] Re: SDRAM data issues -
» [SI-LIST] Re: SDRAM data issues -
» [SI-LIST] SPECCTRAQuest crosstalk question -
» [SI-LIST] Looking for Fast Ethernet IBIS File -
» [SI-LIST] Re: SDRAM data issues -
» [SI-LIST] SDRAM data issues -
» [SI-LIST] FastHenry question -
» [SI-LIST] Re: look for books -
» [SI-LIST] look for books -
» [SI-LIST] RMCEMC May20th Meeting Announcement -
» [SI-LIST] Re: current in a 12 mil via. -
» [SI-LIST] Re: current in a 12 mil via. -
» [SI-LIST] Re: Interfacing SRAM with Intel PRocessor -
» [SI-LIST] current in a 12 mil via. -
» [SI-LIST] Re: Interfacing SRAM with Intel PRocessor -
» [SI-LIST] Interfacing SRAM with Intel PRocessor -
» [SI-LIST] J.L. Prince (Influcence of a floating plane......) Arizona university -
» [SI-LIST] (no subject) -
» [SI-LIST] Re: clipped sine wave output -
» [SI-LIST] Re: Copper Thieving -
» [SI-LIST] Re: Copper Thieving (was: "checkered" copper plane question) -
» [SI-LIST] Copper Thieving (was: "checkered" copper plane question) -
» [SI-LIST] Re: "checkered" copper plane question -
» [SI-LIST] Re: clipped sine wave output -
» [SI-LIST] Re: "checkered" copper plane question -
» [SI-LIST] Re: "checkered" copper plane question -
» [SI-LIST] Re: "checkered" copper plane question -
» [SI-LIST] Re: "checkered" copper plane question -
» [SI-LIST] Re: "checkered" copper plane question -
» [SI-LIST] "checkered" copper plane question -
» [SI-LIST] Re: clipped sine wave output -
» [SI-LIST] Re: Flight Time Approximation -
» [SI-LIST] IBIS Models for CPCI connectors -
» [SI-LIST] EMC/SI course for 2003/2004 -
» [SI-LIST] problem with DC-offset or dynamic range of FDTD code = same post but withcorrect subject -
» [SI-LIST] clipped sine wave output -
» [SI-LIST] question concerning socket for SDRAM module - mechanical problem? -
» [SI-LIST] Re: Flight Time Approximation -
» [SI-LIST] Looking for Mike D. -
» [SI-LIST] Re: Hspice related question -
» [SI-LIST] Re: Hspice related question -
» [SI-LIST] Re: Hspice related question -
» [SI-LIST] SCV EMC May 13th meeting -
» [SI-LIST] Announcing our May 20th meeting -
» [SI-LIST] Re: Hspice related question -
» [SI-LIST] IEEE Dallas EMC looking for technical speakers/experts -
» [SI-LIST] Re: regarding Tprop definition in PCI -
» [SI-LIST] Re: Flight Time Approximation -
» [SI-LIST] Hspice related question -
» [SI-LIST] Re: resonant slot in waveguide, is the hfss admittance matrix -
» [SI-LIST] Flight Time Approximation -
» [SI-LIST] regarding Tprop definition in PCI -
» [SI-LIST] RMCEMC Meeting reminder -
» [SI-LIST] Hspice/spectreS related question -
» [SI-LIST] Help on SI issues -
» [SI-LIST] Re: Do you have this paper about power distribution design? -
» [SI-LIST] Silicon Valley Chapter - Speaker: Lee Ritchey -
» [SI-LIST] Re: Looking for IBIS model of PCI diode terminator -
» [SI-LIST] Re: SSO using IBIS in HSPICE -
» [SI-LIST] SSO using IBIS in HSPICE -
» [SI-LIST] Re: current carrying capacity of Via with time -
» [SI-LIST] current carrying capacity of Via with time -
» [SI-LIST] Re: Questions On Genesys -
» [SI-LIST] Re: resonant slot in waveguide, is the hfss admittance matrix reliable? -
» [SI-LIST] Re: resonant slot in waveguide, is the hfss admittance matrix reliable? -
» [SI-LIST] Re: Looking for IBIS model of PCI diode terminator -
» [SI-LIST] Looking for IBIS model of PCI diode terminator -
» [SI-LIST] resonant slot in waveguide, is the hfss admittance matrix reliable? -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] How to use Protel Signal Integrity Tool -
» [SI-LIST] Do you have this paper about power distribution design? -
» [SI-LIST] 2 month contract in Ottawa -
» [SI-LIST] IBIS of THC63DV164, DVI transmitter from THine Electronics -
» [SI-LIST] PWB paths that penetrate multiple planes -
» [SI-LIST] [OT] Extreme vibration electronics -
» [SI-LIST] Questions On Genesys -
» [SI-LIST] Re: Looking for Spectrum Analyzer info -
» [SI-LIST] Re: Looking for Spectrum Analyzer info -
» [SI-LIST] Un-used differential-paired clock pin termination -
» [SI-LIST] Re: Looking for Spectrum Analyzer info -
» [SI-LIST] test -
» [SI-LIST] Re: Difference betweem single stripline & dual stripline -
» (no subject) -
» [SI-LIST] test -
» [SI-LIST] Re: Five Wire Formula in Wadell -
» [SI-LIST] Crystal Oscillator model search. -
» [SI-LIST] Re: Difference betweem single stripline & dual stripline -
» [SI-LIST] Sampling White Noise -
» [SI-LIST] Re: Five Wire Formula in Wadell -
» [SI-LIST] Re: Five Wire Formula in Wadell -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] Five Wire Formula in Wadell -
» [SI-LIST] Re: Difference betweem single stripline & dual stripline -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] Re: Difference betweem single stripline & dual stripline -
» [SI-LIST] Re: Difference betweem single stripline & dual stripline -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] Difference betweem single stripline & dual stripline -