[SI-LIST] I/O standard flexibility


Hello !=20

 We are developing a general purpose board ( FPGA ).
 For this, we require to support SSTL ( class I & II ) as well as HSTL (
class I & II ) on the same board and same tracks ( the FPGA supports
these standards ). =20
We are looking for an option to give this flexibility without doing any
rework with respect to termination resistor mounting ( As the number of
I/Os are high). We can change the Vref for the same. The series
resistors ( for SSTL ) is present internal to the FPGA ( it can be
programmed to for presence or absence. )=20
I wanted to know if anybody has worked /thought on such a requirement
and to what extent it is possible with respect to SI ?=20
Thanks in advance !=20


Regards,
Pushpraj=20


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