[SI-LIST] Re: Question on DDR SDAM timing spec

Eric,
If the *range* of CK-DQS return roundtrip looptime (RTLP) is less than 1-CK 
period
in duration between lightest and heaviest loading conditions, then theoretically
there exists an ideal DQ/DQS receiver enable time (relative to controller CK 
domain)
which works for all DIMM configurations (because READ preamble is 1-CK wide).

Calculating RTLP involves summing CK delay from controller to DRAMs, DRAM CK-DQS
output skew (tDQSCK), and READ DQS delay from DRAM to controller (over all 
loading/
operating conditions). Some of the delay is on-chip and some off-chip.

The controller can be designed with a range of settings for DQ/DQS receiver
enable with the best setting chosen from a priori RTLP timing prediction or
later with sweep of register settings in lab characterization.

DQ/DQS receiver disable generally is a fixed delay from a particular DQS edge
(like the last or 2nd to last).

There are more elaborate ways to measure RTLP for each DIMM and increase timing
precision for READ DQ/DQS receiver enable/disable, but they are generally
unnecessary at DDR-I speeds.

-jd



--- Eric Deys <edeys@xxxxxxxxxx> wrote:
> Jonathan,
> 
> So, you've said that controller guys hate the asynchronous arrival of this 
> read
> DQS because it's not synchronous to the CK clock!  How are people dealing with
> this in their controllers?  I have my way but thought it would be interesting 
> to
> get different ideas.
> 
> Apparently GDDR solves this with unidirectional DQS's which float to the same
> state as the preamble.  The controller guys should be all over this!!!
> 
> Eric Deys
> 
> Jonathan Dowling wrote:
> 
> > DQS preamble for WRITE transaction is generally 1/2-CK
> > in duration. This guarantees a minimum tWPRE = 1/4-CK
> > for minimum tDQSS = 0.75-CK.
> >
> > DQS receiver enable/disable is more of an issue for READ
> > transaction because DQS signal arrives at controller
> > asynchronously to CK. (Controller guys hate this and
> > its even more of a problem for DDR-II.)
> >
> > -jd
> >
> > --- Chris Cheng <chris.cheng@xxxxxxxxxxxx> wrote:
> > > Hi there,
> > >
> > > I am a little confused in the JEDEC DDR SDRAM timing spec and some of its
> > > electrical implications.
> > >
> > > Here's my original thought :
> > > 1) During bus idle the SSTL_2 input level will be floating round vddq/2
> > > 2) DQS receivers do not like input level being vddq/2, it will either
> > > oscillate or sense an incorrect logic level. Either the receivers have to 
> > > be
> > > disabled or data that gets clocked in has to be discarded
> > > 3) DDR DRAM spec uses tDQSS to defined the absolute arrive time of DQS
> > > w.r.t. the DRAM input ck/ck#. It can arrive as late as 1.25tCK or as early
> > > as 0.75tCK.
> > > 4) DRAM control logic has to assume the DQS within this time is valid
> > > 5) However, the preamble time for write tWPRE only requires the DQS to be
> > > parked to low level at a minimum of 0.25tCK before the first rising edge 
> > > of
> > > tDQS.
> > > 6) This means, in a limiting case, a memory controller can send the DQS to
> > > the target DRAM as late as 1.25tCK (maybe due to heavy loading, DRAM clock
> > > being too early etc) while keeping the bus floating all the way till 
> > > 1.00tCK
> > > (thus meeting the 0.25tCK tWPRE requirement).
> > > 7) However, the poor DRAM DQS receiver has to assume anything arrive after
> > > 0.75tCK as valid strobe signal. Thus between 0.75-1tCK, the DQS input is
> > > floating at VDDQ/2 and god knows what kind of glitch exist at the output 
> > > of
> > > the DQS receiver that will be used to latch in garbage/extra data.
> > >
> > > I am sure a lot of smart people come out with this spec and I make a 
> > > mistake
> > > somewhere in this argument. Can someone point it out to me ?
> > > Thanks in advanced,
> > > Chris
> > >
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> --
> Eric Deys
> Senior IC Design Engineer
> Video Products Division
> Gennum Corporation
> 3430 South Service Road
> Burlington, L7N 3T9
> edeys@xxxxxxxxxx
> (905) 632-2999 x 3200
> 
> 


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