[SI-LIST] Re: Question on DDR SDAM timing spec

All,
This is purely a response to the read timing budget issue.  
In a previous post (see the thread subj: DDR DRAM) I offered these 
links for the ctlr-sourced read-clock case, which I assume is valid here: 


Termination for Point-to-Point Systems
http://www.micron.com/products/technote.jsp?path=/DRAM/DDR+SDRAM&fileID=584

DDR SDRAM timing budget....   it's a long read  
http://download.micron.com/pdf/pubs/designline/dl399.pdf
http://download.micron.com/pdf/pubs/designline/DL92b.pdf

---------------------------------------------------------------

Beyond the Micron info, a quick review suggests a combination of 

1. Ctlr on-chip osc and DLL  and
2. board level DLL (and zero-delay buffer for fanout if needed)

for implementing CLK to the DRAM can mitigate the read cycle 
uncertainties on and off the ctlr chip.  The full details, however, will 
cost 'ya.  

I don't represent that all these elements have the timing tolerances to 
do the job, though. The above Micron info pertaining to ctlr on-chip 
delay lines still applies.  However, the combination of on and off-chip 
elements may complicate the powerup calibration of ctlr delay lines. 

-John


  ----- Original Message ----- 
  From: Eric Deys 
  To: jdowlin2@xxxxxxxxx 
  Cc: si-list@xxxxxxxxxxxxx 
  Sent: Monday, July 14, 2003 1:39 PM
  Subject: [SI-LIST] Re: Question on DDR SDAM timing spec


  Jonathan,

  So, you've said that controller guys hate the asynchronous arrival of this 
read
  DQS because it's not synchronous to the CK clock!  How are people dealing with
  this in their controllers?  I have my way but thought it would be interesting 
to
  get different ideas.

  Apparently GDDR solves this with unidirectional DQS's which float to the same
  state as the preamble.  The controller guys should be all over this!!!

  Eric Deys

  Jonathan Dowling wrote:

  > DQS preamble for WRITE transaction is generally 1/2-CK
  > in duration. This guarantees a minimum tWPRE = 1/4-CK
  > for minimum tDQSS = 0.75-CK.
  >
  > DQS receiver enable/disable is more of an issue for READ
  > transaction because DQS signal arrives at controller
  > asynchronously to CK. (Controller guys hate this and
  > its even more of a problem for DDR-II.)
  >
  > -jd
  >
  > --- Chris Cheng <chris.cheng@xxxxxxxxxxxx> wrote:
  > > Hi there,
  > >
  > > I am a little confused in the JEDEC DDR SDRAM timing spec and some of its
  > > electrical implications.
  > >
  > > Here's my original thought :
  > > 1) During bus idle the SSTL_2 input level will be floating round vddq/2
  > > 2) DQS receivers do not like input level being vddq/2, it will either
  > > oscillate or sense an incorrect logic level. Either the receivers have to 
be
  > > disabled or data that gets clocked in has to be discarded
  > > 3) DDR DRAM spec uses tDQSS to defined the absolute arrive time of DQS
  > > w.r.t. the DRAM input ck/ck#. It can arrive as late as 1.25tCK or as early
  > > as 0.75tCK.
  > > 4) DRAM control logic has to assume the DQS within this time is valid
  > > 5) However, the preamble time for write tWPRE only requires the DQS to be
  > > parked to low level at a minimum of 0.25tCK before the first rising edge 
of
  > > tDQS.
  > > 6) This means, in a limiting case, a memory controller can send the DQS to
  > > the target DRAM as late as 1.25tCK (maybe due to heavy loading, DRAM clock
  > > being too early etc) while keeping the bus floating all the way till 
1.00tCK
  > > (thus meeting the 0.25tCK tWPRE requirement).
  > > 7) However, the poor DRAM DQS receiver has to assume anything arrive after
  > > 0.75tCK as valid strobe signal. Thus between 0.75-1tCK, the DQS input is
  > > floating at VDDQ/2 and god knows what kind of glitch exist at the output 
of
  > > the DQS receiver that will be used to latch in garbage/extra data.
  > >
  > > I am sure a lot of smart people come out with this spec and I make a 
mistake
  > > somewhere in this argument. Can someone point it out to me ?
  > > Thanks in advanced,
  > > Chris
  > >
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  --
  Eric Deys
  Senior IC Design Engineer
  Video Products Division
  Gennum Corporation
  3430 South Service Road
  Burlington, L7N 3T9
  edeys@xxxxxxxxxx
  (905) 632-2999 x 3200


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