Posts for si-list, 08-2003

Browse: Last Month: 07-2003 Main Archive Page Next Month: 09-2003

» [SI-LIST] O.T. Thermodynamics was FEM/BEM/MoM -
» [SI-LIST] Re: Model of Capacitors -
» [SI-LIST] - Signal Integrity Web Seminar - -
» [SI-LIST] Serial ATA PWB Design guidelines -
» [SI-LIST] Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] Fwd: Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] Re: Crowbar current in push-pull drivers -
» [SI-LIST] High speed ADCs modelling -
» [SI-LIST] Crowbar current in push-pull drivers -
» [SI-LIST] Overview of Modeling Techniquess - a link -
» [SI-LIST] Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. -
» [SI-LIST] Re: 2D field solvers -
» [SI-LIST] Re: FEM/BEM/MoM -
» [SI-LIST] Re: FEM/BEM/MoM -
» [SI-LIST] 2D field solvers -
» [SI-LIST] Regarding Signal Integrity Training -
» [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. -
» [SI-LIST] Re: Model of Capacitors -
» [SI-LIST] Model of Capacitors -
» [SI-LIST] Re: Scaling the HSPICE netlist -
» [SI-LIST] Re: FEM/BEM/MoM -
» [SI-LIST] Re: FEM/BEM/MOM -
» [SI-LIST] Re: Scaling the HSPICE netlist -
» [SI-LIST] Re: OT: e-mail encoding? (was; Via Inductance Formula Assumptions) -
» [SI-LIST] Re: FEM/BEM/MOM -
» [SI-LIST] Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] Scaling the HSPICE netlist -
» [SI-LIST] Re: heat v. radiation Re: FEM/BEM/MoM -
» [SI-LIST] Re: FEM/BEM/MoM -
» [SI-LIST] FEM/BEM/MoM -
» [SI-LIST] ICX vs Spectraquest question -
» [SI-LIST] OT: e-mail encoding? (was; Via Inductance Formula Assumptions) -
» [SI-LIST] Re: FEM/BEM/MoM -
» [SI-LIST] Re: Via Inductance Formula Assumptions -
» [SI-LIST] FEM/BEM/MoM -
» [SI-LIST] Re: Via Inductance Formula Assumptions -
» [SI-LIST] Re: Via Inductance Formula Assumptions -
» [SI-LIST] Re: FEM/BEM/MOM -
» [SI-LIST] layout recommendation? -
» [SI-LIST] RJ-45 JACK with Integrated Magnetics -
» [SI-LIST] Re: FEM/BEM/MOM -
» [SI-LIST] Re: FEM/BEM/MOM -
» [SI-LIST] UNSUBSCRIBE -
» [SI-LIST] FEM/BEM/MOM -
» [SI-LIST] Re: Via Inductance Formula Assumptions -
» [SI-LIST] Via Inductance Formula Assumptions -
» [SI-LIST] Re: cross talk (direction of E-Filed) -
» [SI-LIST] Re: cross talk (direction of E-Filed) -
» [SI-LIST] placement (RF + Digital) -
» [SI-LIST] cross talk (direction of E-Filed) -
» [SI-LIST] PCB Fabrication Compensation -
» [SI-LIST] Transmission line behaviour on-chip interconnects -
» [SI-LIST] Test -
» [SI-LIST] Looking for a Job as SI/Simulation Engineer. -
» [SI-LIST] AW: Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] [Fwd: PCB power distrbution analysis tools] -
» [SI-LIST] Re: Cadence Spectre Waveforms -
» [SI-LIST] UMR EMC course comes to Colorado -
» [SI-LIST] RMCEMC August Meeting Reminder -
» [SI-LIST] Ground Bounce and Bypass. -
» [SI-LIST] Re: W-element in hspice -
» [SI-LIST] Re: W-element in hspice -
» [SI-LIST] Re: W-element in hspice -
» [SI-LIST] Re: Transmission line behaviour of on-chip interconnects -
» [SI-LIST] W-element in hspice -
» [SI-LIST] Transmission line behaviour of on-chip interconnects -
» [SI-LIST] Re: DDR-II SDRAM (SSTL-18 class-II): AC-test load -
» [SI-LIST] Airbox sensitivity for gap source port -
» (no subject) -
» [SI-LIST] Re: LVDS -
» [SI-LIST] Airbox sensitivity for gap source port -
» [SI-LIST] Re: Cadence Spectre Waveforms -
» [SI-LIST] HSPICE for Hyperlynx GHZ -
» [SI-LIST] Cadence Spectre Waveforms -
» [SI-LIST] Microelectronic Packaging Class - Fall 03 at SJSU -
» [SI-LIST] Re: DataSheet to IBIS -
» [SI-LIST] Re: characterizing interconnect structures with s-parameter -
» [SI-LIST] Re: characterizing interconnect structures with s-parameter -
» [SI-LIST] Re: DataSheet to IBIS -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] Re: ECHO cancellation hybrid -
» [SI-LIST] Re: characterizing interconnect structures with s-parameter -
» [SI-LIST] Re: characterizing interconnect structures with s-parameter -
» [SI-LIST] Re: ECHO cancellation hybrid -
» [SI-LIST] ECHO cancellation hybrid -
» [SI-LIST] characterizing interconnect structures with s-parameter -
» [SI-LIST] Interpolative A/D -
» [SI-LIST] Die Probe Machine Users Manual manual -
» [SI-LIST] Re: Switching point -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] LVDS -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass CapacitorCaculator) -
» [SI-LIST] Switching point -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: About SpecctraQuest Crosstalk Simulation -
» [SI-LIST] Re: Sobig-F virus -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] Re: AC coupling hspice simulation -
» [SI-LIST] Re: Phase/Frequency Detector! -
» [SI-LIST] Phase/Frequency Detector! -
» [SI-LIST] Sobig-F virus -
» [SI-LIST] Re: AC coupling hspice simulation -
» [SI-LIST] Re: AC coupling hspice simulation -
» [SI-LIST] Re: AC coupling hspice simulation -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: SSTL2 ClassI and ClassII -
» [SI-LIST] via loss characterization -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Call for Presentations - BiTS (Burn-in & Test Socket) Workshop, March 7-10 2004, Mesa Arizona -
» [SI-LIST] Signal Integrity Engineer-Bay area 8-18 -
» [SI-LIST] Re: zero ohm jumper spice models ?? -
» [SI-LIST] AC coupling hspice simulation -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] field solvers -
» [SI-LIST] Re: zero ohm jumper spice models ?? -
» [SI-LIST] to calculate the cell leakage power -
» [SI-LIST] Whether can I combine deferent segments in the path description of ebd file into one -
» [SI-LIST] Re: R L & C extraction -
» [SI-LIST] About SpecctraQuest Crosstalk Simulation -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] zero ohm jumper spice models ?? -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] Re: SI software for Cadence -
» [SI-LIST] SI software for Cadence -
» [SI-LIST] Re: R L & C extraction -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: R L & C extraction -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - 9/3 meeting announcement -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: R L & C extraction -
» [SI-LIST] R L & C extraction -
» [SI-LIST] SSTL2 ClassI and ClassII -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capac itor Caculator) -
» [SI-LIST] FW: Fieldsolvers -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and BypassCapacitor Caculator) -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capac itor Caculator) -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR andBypassCapacitor Caculator) -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Re: Question about simulation with INTEL IBIS file -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] RMCEMC August meeting announcement -
» [SI-LIST] Re: Fieldsolvers -
» [SI-LIST] Fieldsolvers -
» [SI-LIST] Re: Pentium M ??? -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: Pentium M ??? -
» [SI-LIST] Pentium M ??? -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: LVPECL standard ? -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: Question about simulation with INTEL IBIS file -
» [SI-LIST] Re: Question about simulation with INTEL IBIS file -
» [SI-LIST] Question about simulation with INTEL IBIS file -
» [SI-LIST] Re: LVPECL standard ? -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: terminating busses -
» [SI-LIST] Use of package model in SPECCTRAQuest -
» [SI-LIST] Re: LVPECL standard ? -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: SI software question thanks -
» [SI-LIST] Re: SI software question thanks -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] SI software question thanks -
» [SI-LIST] Re: cpw question? -
» [SI-LIST] Re: SI software question -
» [SI-LIST] Re: cpw question? -
» [SI-LIST] LVPECL standard ? -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: On resistance of the driver and the input capacitance of -
» [SI-LIST] Re: si-list 'Reply-to:' function now points to sender -
» [SI-LIST] Re: si-list 'Reply-to:' function now points to sender -
» [SI-LIST] Re: SI software question -
» [SI-LIST] Re: si-list 'Reply-to:' function now points to sender -
» [SI-LIST] Re: SI software question -
» [SI-LIST] Re: si-list 'Reply-to:' function now points to sender -
» [SI-LIST] Re: si-list 'Reply-to:' function now points to sender -
» [SI-LIST] si-list 'Reply-to:' function now points to sender -
» [SI-LIST] Re: SI software question -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: On sharing viewpoints and info -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: jitter on differential pairs -
» [SI-LIST] Re: jitter on differential pairs -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] On sharing viewpoints and info -
» [SI-LIST] Re: LVPECL to SSTL and LVPECL to HSTL -
» [SI-LIST] jitter on differential pairs -
» [SI-LIST] Re: SI software question -
» [SI-LIST] Re: SI software question -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: si-list Digest V3 #231 -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: cpw question? -
» [SI-LIST] Joachim Mueller/WLGORE is out of the office. -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: SI software question -
» [SI-LIST] SI software question -
» [SI-LIST] Re: cpw question? -
» [SI-LIST] Re: LVPECL to SSTL and LVPECL to HSTL -
» [SI-LIST] Re: si-list Digest V3 #231 -
» [SI-LIST] cpw question? -
» [SI-LIST] Re: LVPECL to SSTL and LVPECL to HSTL -
» [SI-LIST] Re: si-list Digest V3 #231 -
» [SI-LIST] Re: On resistance of the driver and the input capacitance of receiver -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] LVPECL to SSTL and LVPECL to HSTL -
» [SI-LIST] Compatible Device -
» [SI-LIST] Can anyone recommend a 2D extractor for on-chip tranmission line? -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Recall: Re: On resistance of the driver and the input capacitance of receiver -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: On resistance of the driver and the input capacitance of receiver -
» [SI-LIST] Re: On resistance of the driver and the input capacitance of receiver -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] On resistance of the driver and the input capacitance of receiver -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Question regarding thermal layers -
» (no subject) -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Question regarding thermal layers -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Question regarding thermal layers -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Protel vs Electronics Workbench -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: LVDS -
» [SI-LIST] Re: LVDS -
» [SI-LIST] Re: Rf measuring -
» [SI-LIST] Super IO Compatible Device -
» [SI-LIST] Re: need help on RLGC -
» [SI-LIST] LVDS -
» [SI-LIST] Need help for Xtalk Problem -
» [SI-LIST] Re: need help on RLGC -
» [SI-LIST] need help on RLGC -
» [SI-LIST] PCI Prototype T1/E1 Adapter Board -
» [SI-LIST] Marc Charbonneau/NNH/Teradyne is out of the office. -
» [SI-LIST] Re: Question regarding thermal layers -
» [SI-LIST] RMCEMC July Meeting Download & Pictures -
» [SI-LIST] Re: Question regarding thermal layers -
» [SI-LIST] Question regarding thermal layers -
» [SI-LIST] Re: Rf measuring -
» [SI-LIST] Rf measuring -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] test -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Re: Protel vs Electronics Workbench -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Re: Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Zodd Differential Calculation for Hspice w-element -
» [SI-LIST] Re: Question on ADS Momentum simulation -
» [SI-LIST] end freelist -
» [SI-LIST] Re: Protel vs Electronics Workbench -
» [SI-LIST] Re: Question on ADS Momentum simulation -
» [SI-LIST] automated response -
» [SI-LIST] Re: Protel vs Electronics Workbench -
» [SI-LIST] Protel vs Electronics Workbench -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: AC overshoot -
» [SI-LIST] AC overshoot -
» [SI-LIST] MAX_CONDUCTOR_NUMBER in Hspice W element -
» [SI-LIST] Does Hspice can do post-simulation on PCB level? -
» [SI-LIST] Does Hspice can do post-simulation on PCB level? -
» [SI-LIST] Require help on GMAC MX98728 Chip -
» [SI-LIST] Re: Interconnect Lumped Modelling -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Innterconnect Lumped modeling -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: Innterconnect Lumped modeling -
» [SI-LIST] Re: Lumped Interconnect Modelling -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Common mode emissions -
» [SI-LIST] Re: IA5 character -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: Question on ADS Momentum simulation -
» [SI-LIST] Re: DC/DC converter output dip -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Interconnect Lumped Modelling -
» [SI-LIST] Question on ADS Momentum simulation -
» [SI-LIST] Re: power supply -
» [SI-LIST] Re: high speed connectors -
» [SI-LIST] Re: high speed connectors -
» [SI-LIST] Re: high speed connectors -
» [SI-LIST] Re: IA5 character -
» [SI-LIST] high speed connectors -
» [SI-LIST] Re: IA5 character -
» [SI-LIST] IA5 character -
» [SI-LIST] DC/DC converter output dip -
» [SI-LIST] Re: HSPICE-MEASUREMENTS -
» [SI-LIST] Re: HSPICE-MEASUREMENTS -
» [SI-LIST] power supply -
» [SI-LIST] Re: si-list Digest V3 #222 -
» [SI-LIST] Re: HSPICE-MEASUREMENTS -
» [SI-LIST] Re: Lumped Interconnect Modelling -
» [SI-LIST] Re: Common mode emissions -
» [SI-LIST] DC Resistance for PCB power plane -
» [SI-LIST] Propagation Delay through a via -
» [SI-LIST] Lumped Interconnect Modelling -
» [SI-LIST] Re: Interconnect Lumped Modelling -
» [SI-LIST] Common mode emissions -
» [SI-LIST] Re: Interconnect Lumped Modelling -
» [SI-LIST] Re: Interconnect Lumped Modelling -
» [SI-LIST] Interconnect Lumped Modelling -
» [SI-LIST] HSPICE-MEASUREMENTS -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: [JunkMail] Re: Sin(x)/x -
» [SI-LIST] Re: [JunkMail] Re: Sin(x)/x -
» [SI-LIST] Re: Sin(x)/x -
» [SI-LIST] Sin(x)/x -
» [SI-LIST] Re: [Negative Circuit elements?] -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Calculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Calculator -
» [SI-LIST] Re: Five emerging technologies that will revolutionize high-speed systems -
» [SI-LIST] Re: Return path and C/S Impedance -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: Return path and C/S Impedance -
» [SI-LIST] Five emerging technologies that will revolutionize high-speed systems -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: More High Speed Design Books -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: [Negative Circuit elements?] -
» [SI-LIST] Re: Conversion from dB to ohm -
» [SI-LIST] Re: threshold and 60 Hz -
» [SI-LIST] formulas for impedance -
» [SI-LIST] connectors.. -
» [SI-LIST] Return path and C/S Impedance -
» [SI-LIST] Re: High Speed Design Books.. -
» [SI-LIST] Re: A question about data mask in SDRAM/DDR -
» [SI-LIST] A question about data mask in SDRAM/DDR -
» [SI-LIST] Re: Coding theory... -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] power distrbution tools -
» [SI-LIST] Coding theory... -
» [SI-LIST] Re: High Speed Design Books.. -
» [SI-LIST] [Negative Circuit elements?] -
» [SI-LIST] Re: Microstrip Inductance (Old Wine in New Bottle) -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Re: threshold -
» [SI-LIST] board weight esitimation -
» [SI-LIST] Re: Quasi Static Assumptions -
» [SI-LIST] Re: threshold and 60 Hz -
» [SI-LIST] Andrew B Maki/Rochester/IBM is out of the office returning on August 4th. -
» [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator -
» [SI-LIST] Antw: how to start high speed PCB design ? -
» [SI-LIST] Re: IBIS packaging models -