[SI-LIST] Re: op-amp compensation capacitor in digital cmos process

Han,

I think you may have to use twice the capacitance to ensure at least on=
e
MOS is on. This will eat up twice the area. Even though you have a trip=
le
well process you have at least on well in a CMOS process. This well can=
 be
isolated form the power supply. We use this "floating" well technique o=
nce
in a while but usually don't have the operating range to use this as a
compensating technique. To insure that  the PMOS Capacitor has enough
Vgs(d) to maintain a channel is usually not possible. That's why I woul=
d
suggest using a big enough PMOS and NMOS  to compensate even if the oth=
er
was not in the circuit. It is a brute force method but it will work wit=
h a
wide operating range.

Bill Cohen
Toshiba America


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                    Bi Han                                             =
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 op-amp compensation capacitor in digital cmos=20
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                    07/15/2003 09:23                                   =
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                    Please respond to                                  =
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                    mike_bihan                                         =
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Bill:
Thanks for your information!
I agree that MOS gate cap is a good idea.
But I may not be able to guarantee the working range of MOS cap in stro=
ng
inversion mode because the gain of the op-amp will be very high.
Meanwhile, there is no triple well process, so all nmos's well is conne=
cted
to substrate, pmos to VCC.

What should I do?
Bill.Cohen@xxxxxxxxxxxxxxxx wrote:

Han,

It may not be a great idea but I compensate all my opamps with MOS gate=

capacitors. Just make sure the device is in saturation otherwise you wi=
ll
get too much series resistance to the thin oxide device. If it is a rai=
l to
rail opamp you may need to used Both NMOS and PMOS devices to keep at l=
east
one device active depending on the common mode. Also, you will only be =
able
to use the device in the well if you need a compensating device with on=
e
end not tied to the power supply.

Bill Cohen
Toshiba America




Bi Han

com.cn> cc:
Sent by: Subject: [SI-LIST] op-amp compensation capacitor in digital cm=
os
si-list-bounce@fre process
elists.org


07/15/2003 07:34
AM
Please respond to
mike_bihan






hi, experts:
I am on a project designing high speed limiter in digital cmos process.=
 I
need to design some op-amp as controlling circuits.
So, I need capacitor to compensate them to stable. But, in my digital c=
mos
process(1p6m), there will be no MIM/PIP capacitor, so I can not compens=
ate
the op-amp!!
Any people have good idea?
Thanks, Han


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