[SI-LIST] Re: Reducing SSO noise in an FPGA

Some additional historical data.

A classical route to noise reduction is a 25 ohm snubber resistor in 
series with the output.
This resistor serves as a series terminator for a transmission line or a 
damping resistor
for the RLC of the lead inductance and a lumped capacitive load. Most 
situations are
somewhere in between these two models. The resistor works anyway for 
equivalent reasons.
 
There are two interesting aspects of the 25 ohm resistor. First, its 
value is tied to the
PCB and typical impedance values of traces and/or inductance-capacitance 
values
that yield a similar impedance for typical RLC resonant circuits.

A value of 25 ohms works well for traces in the 40-70 ohm and up range.
Impedance is typically driven by load pin capacitances more than trace 
inductance.
For lightly loaded lines, the capacitance is low, the impedance is high, 
and you do
not need much noise supression because there is little capacitive energy 
storage.
As the capacitance rises, the impedance drops, you need more 
suppression, and
the 25 ohms becomes relatively more effective as the impedance drops toward
a 25 ohm perfectly terminated line.

A common situation is a 25 ohm resistor into a 40-50 ohm line.
The result is an underterminated line. You get ~25% overshoot and ringing.
However, you also get a higher initial step, which can provide switching
on the first edge. You are trading speed for noise.

The second is that you really want a resistor, not a small driver.
The first reason for this is that it is easier to hold tolerance on a 
resistor
over voltage, temerature and process than to hold the saturation current
and on resistance of a driver over these same variations.

The second reason is that you want a linear resistor, not a current limit.
The function of the resistor is to absorb energy from the capacitance of
the load/transmission line. The resistor typically comes into play *after*
the driver has gone from current limited to resistive, high or low.
Unless you have a very high current driver, the voltage drop across the
resistor during transition will typically be less than the distance from
either rail to threshold. This means that the driver will be in its current
limited mode while the voltage at the resistor output is passing through
threshold. The resistor is not limiting the current in this case and is not
yet absorbing the energy in the transmission line/resonant circuit.

The resistor comes into play after the driver is completely switched high
or low. At this point, energy in the load capacitance is dissipated in the
resistor, either as a terminator dissipating reflected energy from a 
transmission
line or as a linear resistor absorbing energy in an RLC resonant circuit.
Take your choice of models.

In the early 90's, Quality Semiconductor came out with the FCT2000 series
of logic, which was FCT glue logic with built-in 25 ohm resistors. In most
applications, substituting an FCT2000 part for the equivalent FCT part
cut ground bounce noise and system noise in half. Speed actually increased
slightly because of reduced on-chip Vcc droop.

Just a little trivia to lighten your day,

Dave Wyland


Chris Cheng wrote:

>Sure you can, don't you have an external series resistor and parallel
>terminator you can play around their values ?
>
>-----Original Message-----
>From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
>Sent: Tuesday, July 15, 2003 12:58 PM
>To: chris.cheng@xxxxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
>
>I cannot reduce the drive strength, the drivers are SSTL2.  We reduced
>the SSO noise significantly by turning off half the data bits.
>
>-----Original Message-----
>From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx] 
>Sent: Tuesday, July 15, 2003 2:27 PM
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
>What's wrong with reducing the driving strength of the drivers in the
>FPGA ?
>Are you at the limit of the lowest possible drive strength already ?
>
>-----Original Message-----
>From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
>Sent: Tuesday, July 15, 2003 5:54 AM
>To: bhenson@xxxxxxxxxxxx; Ken.Cantrell@xxxxxxxxxxx
>Cc: bill.panos@xxxxxxxxxxxxxxx; Chris Cheng; scott@xxxxxxxxxxxxx;
>si-list@xxxxxxxxxxxxx
>Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
>
>This discussion has turned quite interesting.  There have been several
>comments which imply that the only way to reduce SSO noise in an
>FPGA/ASIC is to add decoupling at the die or inside the package.  These
>are fixes which only the device manufacturers can make.  
>Does anyone have measurement/simulation data on what effect adding many
>decoupling capacitors under the BGA package, between VCC and ground
>balls, will have on the SSO noise?
>
>Thanks and regards, 
>Fabrizio
>
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