[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: Mark Alexander <mark.alexander@xxxxxxxxxx>
- To: Ken.Cantrell@xxxxxxxxxxx
- Date: Thu, 17 Jul 2003 13:57:51 -0700
Or go to a different standard altogether -- the various flavors of LVCMOS
and LVDCI have fairly fine granularity in drive strength.
-mark
Ken Cantrell wrote:
> Or go to a class 1 if you are using a class 2 (7.2 mA vs 15.7 ma)
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
> Sent: Tuesday, July 15, 2003 2:09 PM
> To: 'Fabrizio Zanella'; Chris Cheng
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
> Sure you can, don't you have an external series resistor and parallel
> terminator you can play around their values ?
>
> -----Original Message-----
> From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
> Sent: Tuesday, July 15, 2003 12:58 PM
> To: chris.cheng@xxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
> I cannot reduce the drive strength, the drivers are SSTL2. We reduced
> the SSO noise significantly by turning off half the data bits.
>
> -----Original Message-----
> From: Chris Cheng [mailto:chris.cheng@xxxxxxxxxxxx]
> Sent: Tuesday, July 15, 2003 2:27 PM
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
> What's wrong with reducing the driving strength of the drivers in the
> FPGA ?
> Are you at the limit of the lowest possible drive strength already ?
>
> -----Original Message-----
> From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]
> Sent: Tuesday, July 15, 2003 5:54 AM
> To: bhenson@xxxxxxxxxxxx; Ken.Cantrell@xxxxxxxxxxx
> Cc: bill.panos@xxxxxxxxxxxxxxx; Chris Cheng; scott@xxxxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
> This discussion has turned quite interesting. There have been several
> comments which imply that the only way to reduce SSO noise in an
> FPGA/ASIC is to add decoupling at the die or inside the package. These
> are fixes which only the device manufacturers can make.
> Does anyone have measurement/simulation data on what effect adding many
> decoupling capacitors under the BGA package, between VCC and ground
> balls, will have on the SSO noise?
>
> Thanks and regards,
> Fabrizio
>
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