[SI-LIST] QDRII FPGA design

I am in process of designing a QDRII interface test system. One of the
options is to do this using an FPGA as the interface. Does anyone have
any experience or comments about doing this? I have seen app notes
regarding the QDRI interface but only up to 200MHz. I am looking to run
faster (up to 500MHz) than that. I am not currently tied to any specific
FPGA or architecture. Currently it looks as though I can not implement
the QDRII interface at any higher than 200MHz on an FPGA.

Thank you for your time,

Chris

--
Christopher Betz                Integrated Device Technology
Test Engineer                   11555 Medlock Bridge Road
Atlanta Design Center           Suite 200
Christopher.Betz@xxxxxxx        Duluth, GA 30097
678/775-2978




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