[SI-LIST] Re: MOS cap on chip for DECOUPLING
- From: Steve Horne <sch@xxxxxxxxxxxxxx>
- To: rajat@xxxxxxxxxxxx
- Date: Wed, 23 Jul 2003 08:43:46 -0500
Rajat Chauhan writes:
> Bi Han wrote:
> >
> > Hi, experts:
> >
> > In CMOS technology, what's the difference between using MOS cap as VCC
> > decoupling in three different ways?
> >
> > 1. NMOS --> gate to VCC, other three nodes to VSS (inversion)
This is not bad, as long as VCC is significantly above the
n-channel threshold voltage. As you approach a Vt, the
capacitance will drop.
> >
> > 2. PMOS --> gate to VCC, other three nodes to VSS (accumulation)
This is actually not in accumulation - the p-channel is in
depletion (i.e., it is in its normal off-state). This would be a
rather poor capacitor compared to an inversion or accumulation
capacitor.
> >
> > 3. PMOS --> gate to vss, other three nodes to VCC ( inversion)
Like the first case, this would be a reasonable capacitor.
Depending on the capacitor geometry, it has a disadvantage
compared to the first option. The hole mobility is lower than
that of electrons, so you will see a larger ESR for this
capacitor than the first one.
> >
> > What's their difference in High frequency application such as high speed
> > limiting amplifier?
I don't know much about that. I'm coming from a microprocessor
decoupling perspective.
> >
> > Thanks!
> >
> >
> > ---------------------------------
> I would like to add one more to it:
>
> 4. NMOS --> gate, drain and source to VCC, Bulk to VSS.
This would not be a great capacitor, because the channel is not
at ground. Because you are not getting the maximum voltage
across the thin gate oxide, you will get less capacitance from
the gate. However, you pick up a little source/drain to bulk
capacitance, depending on the process technology. Not as good a
choice as #1 or #3, IMO.
Yet another option (assuming you have this option in your fab
process) is
5. Varactor --> for example, an n-channel transistor in an N-well
with n+ source and drains, gate tied to VSS and
source/drain/well tied to ground. This seems kind of weird,
but it is a MOSFET that is truly in accumulation. This will
give you similar capacitance than #1, but you can let VCC
approach a Vt without seeing the capacitance drop. The ESR of
this capacitor is also fairly low, which is good (though maybe
someone would actually want a higher ESR to reduce a parallel
resonance, I don't know).
BTW, the ESR of all these capacitors and the ideal geometry
depends partly on whether you are in a p substrate of an n
substrate (or SOI). It also depends on your poly gate
resistivity compared to your channel resistance. You have to
select a capacitor that is suited to your fab process.
A couple of other issues that affect your choice of capacitor
type and geometry are
- leakage at your expected operating voltage
- defect density at the field/diffusion edges vs in the middle
of the gate
Steve
>
> Thanks
> Rajat
> ___________________________
> RAJAT CHAUHAN
> TI-Banglore
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