[SI-LIST] Re: least inductance path(return current)

Karan:
The paper by Larry Smith (epep_1999.pdf) in the yahoo files library for
this list discusses this issue in detail. The give a short answer to
your question, yes, the return current is on the top of the power plane
on layer 2. Therefore, if the drivers force the return current to flow
on the ground line (e.g., during a high-to-low transition for a CMOS
driver), a return path discontinuity or RPD occurs around the driver.
This RPD could be reduced by a decoupling capacitor near the driver,
otherwise parallel-plate mode will be excited between the planes in
addition to the intended microstrip mode, causing power/ground noise.

Ege

karan bagga schrieb:
> 
> This is a very basic doubt:
> 
> SI Book says that return current follows the "least inductance path"
> 
> Now supposingly i have the following stack up
> 
> 1) signal
> 
> 2) power
> 
> 3) signal
> 
> 4) gnd
> 
> 5) signal
> 
> If i have atrack on layer 1.
> 
> Supposingly the circuit loops gets completed with the gnd on layer 4.
> 
> What will the return current path ?
> 
> Suppose there are ByPass caps also b/w power(2) and gnd(4).
> 
> "Some books says the return current will first go to power and then through 
> bypass
> 
> to gnd". Is it correct ?
> 
> Can you please tell me why this happens ?
> 
> Even if my circuit does not include power(2)
> 
> why would current flow through it? ( i know i am missing something, need 
> help)..
> 
> Thanks for the explanation
> 
> 
> 
> Regards
> 
> Karan
> 
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