[SI-LIST] Re: Reducing SSO noise in an FPGA
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Jack Stone" <mediwheel_js@xxxxxxxxx>,"Chris Cheng" <chris.cheng@xxxxxxxxxxxx>
- Date: Thu, 17 Jul 2003 08:45:42 -0700
SSO noise is a package problem that cannot be fixed with any kind of
capacitance on the PCB. The package must be redesigned.
Lee
Lee Ritchey
leeritchey@xxxxxxxxxxxxx
Why Wait? Move to EarthLink.
> [Original Message]
> From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
> To: Jack Stone <mediwheel_js@xxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 7/16/2003 1:39:06 PM
> Subject: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
> Wow,
> I would sure like to learn how could an external capacitor on a PCB can be
> effective on reducing SSO noise on a highspeed system. Especially if it is
> placed underneath the package on a PCB and have to go through the PCB via,
> pad, package via inductance. Could you please educate me ?
>
> -----Original Message-----
> From: Jack Stone [mailto:mediwheel_js@xxxxxxxxx]
> Sent: Wednesday, July 16, 2003 1:04 PM
> To: fzanella@xxxxxxxxxxxx; bhenson@xxxxxxxxxxxx;
> Ken.Cantrell@xxxxxxxxxxx
> Cc: bill.panos@xxxxxxxxxxxxxxx; Chris Cheng; scott@xxxxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Reducing SSO noise in an FPGA
>
>
> Fabrizio,
>
> Yes this has been done in extreme cases whereby the analysis of the
> drivers/receivers, package stackup, routing, power distribution and proper
> noise immunity failed in the initial design of an ASIC. Or in some cases
was
> not performed at all. The offset is enough to allow an 0603 with
acceptable
> results. However reworkability and process errors can wreak havoc on your
> DPM's once the product goes out to market.
>
> jack ~
>
>
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