Posts for si-list, 05-2006

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» [SI-LIST] Re: PCI-X (133Mhz) bus terminations -
» [SI-LIST] Re: PCI-X (133Mhz) bus terminations -
» [SI-LIST] PCI-X (133Mhz) bus terminations -
» [SI-LIST] Re: Terminations Query -
» [SI-LIST] Re: Terminations Query -
» [SI-LIST] Re: Terminations Query -
» [SI-LIST] Re: Copper balancing -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] Terminations Query -
» [SI-LIST] Re: Copper balancing -
» [SI-LIST] Re: Copper balancing -
» [SI-LIST] Stackup issue -
» [SI-LIST] Copper balancing -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] measurement methods of power supply networks for a wirebond BGA package -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Re: Common-mode return loss in Hspice -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] gigabit ethernet trace length -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: Common-mode return loss in Hspice -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes/"tools to predict Radiated Emissions" -
» [SI-LIST] Re: Decoupling Capacitor for LNA and PA -
» [SI-LIST] Re: Decoupling Capacitor for LNA and PA -
» [SI-LIST] Re: Loss Tangent -
» [SI-LIST] Re: Decoupling Capacitor for LNA and PA -
» [SI-LIST] Decoupling Capacitor for LNA and PA -
» [SI-LIST] Re: Reg: No of Decoupling capacitors -
» [SI-LIST] Re: Reg: No of Decoupling capacitors -
» [SI-LIST] Reg: No of Decoupling capacitors -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Re: Loss Tangent -
» [SI-LIST] Re: Loss Tangent -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Re: Loss Tangent -
» [SI-LIST] Re: Loss Tangent -
» [SI-LIST] Loss Tangent -
» [SI-LIST] Workshop on verification and troubleshooting of designs -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Re: Common-mode return loss in Hspice -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes - a history -
» [SI-LIST] Common-mode return loss in Hspice -
» [SI-LIST] Re: TDR -
» [SI-LIST] TDR -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Question about split gnd planes - a history -
» [SI-LIST] Re: How good are tools to predict Radiated Emissions ? -
» [SI-LIST] How good are tools to predict Radiated Emissions ? -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Low-Q Controlled-ESR Bypass Capacitors -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] Re: Low-Q Controlled-ESR Bypass Capacitors -
» [SI-LIST] Significance of Frequency -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Question about split gnd planes -
» [SI-LIST] Re: test board -
» [SI-LIST] Re: test board -
» [SI-LIST] Re: test board -
» [SI-LIST] Re: test board -
» [SI-LIST] Low-Q Controlled-ESR Bypass Capacitors -
» [SI-LIST] test board -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: AC coupling Capacitor -
» [SI-LIST] AC coupling Capacitor -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Two Job openings at PLX technology -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] SMA vs. SSMA vs. both? -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: help -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Capacitors arrays?worth it or not? -
» [SI-LIST] help -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB stackup -
» [SI-LIST] Re: PCB stackup -
» [SI-LIST] Re: is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Capacitors arrays?worth it or not? -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB stackup -
» [SI-LIST] Re: Capacitors arrays… worth it or not? -
» [SI-LIST] Re: is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Re: is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Re: PCB stackup -
» [SI-LIST] Re: is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: [SPAM] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Ring back -
» [SI-LIST] is clock pair-to-clock pair matching required in DDR? -
» [SI-LIST] Hello everybody...!!! -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: FW: Re: Ring back -
» [SI-LIST] FW: Re: Ring back -
» [SI-LIST] Recall: Re: Ring back -
» [SI-LIST] Recall: Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: PCB Reverse Engineering we could stop it -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB Reverse Engineering we could stop it -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB Reverse Engineering we could stop it -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Resistive Leakage Paths -
» [SI-LIST] Re: Resistive Leakage Paths -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Re: Resistive Leakage Paths -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Ring back -
» [SI-LIST] Re: PCB Warpage during Assembly -
» [SI-LIST] Ring back -
» [SI-LIST] PCB Warpage during Assembly -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays? worth it or not? -
» [SI-LIST] Re: Capacitors arrays? worth it or not? -
» [SI-LIST] Re: Modeling for Transformer in E1/T1 -
» [SI-LIST] Modeling for Transformer in E1/T1 -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays? worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: the measurement of inductances or bea ds -
» [SI-LIST] Re: the measurement of inductances or bea ds -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Re: Capacitors arrays. worth it or not? -
» [SI-LIST] Apple Computer has a Sr. SI Engineer opening -
» [SI-LIST] Re: Signal Integrity issues at -40 degrees C -
» [SI-LIST] Re: Capacitors arrays? worth it or not? -
» [SI-LIST] Re: [SPAM] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Signal Integrity issues at -40 degrees C -
» [SI-LIST] Re: Signal Integrity issues at -40 degrees C -
» [SI-LIST] Re: Signal Integrity issues at -40 degrees C -
» [SI-LIST] Re: Capacitors arrays… worth it or not? -
» [SI-LIST] SI job openings in Cisco San Jose -
» [SI-LIST] Capacitors arrays? worth it or not? -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Resistive Leakage Paths -
» [SI-LIST] Re: Signal Integrity issues at -40 degrees C -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Signal Integrity issues at -40 degrees C -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Re: BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] BoardScan by Quantic and HyperLynx by Mentor -
» [SI-LIST] Re: [SPAM] Re: PCB Reverse Engineering -
» [SI-LIST] Re: guard traces - sata / pcie -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: guard traces - sata / pcie -
» [SI-LIST] Inexpensive Sources of Useful Test Equipment -
» [SI-LIST] Re: [SPAM] Re: PCB Reverse Engineering -
» [SI-LIST] guard traces - sata / pcie -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: the measurement of inductances or beads -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] the measurement of inductances or beads -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: [½ðÉ½¶¾°ÔÊ¶±ð´ËÓÊ¼þÎªÀ¬»øÓÊ¼þ]Re: LVCMOS Trace length for 106MHz Clock -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: LVCMOS Trace length for 106MHz Clock -
» [SI-LIST] Re: LVCMOS Trace length for 106MHz Clock -
» [SI-LIST] Re: LVCMOS Trace length for 106MHz Clock -
» [SI-LIST] Re: LVCMOS Trace length for 106MHz Clock -
» [SI-LIST] LVCMOS Trace length for 106MHz Clock -
» [SI-LIST] PCB Reverse Engineering -
» [SI-LIST] Re: Web cast seminars -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Dell SI job openings -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: Board Design Lead Position Available at San Jose Company (perm/fulltime) -
» [SI-LIST] Signal Integrity Engineer Position Available/ San Jose -
» [SI-LIST] Board Design Lead Position Available at San Jose Company (perm/fulltime) -
» [SI-LIST] Signal Integrity Engineer Position Available at San Jose Company (perm/fulltime) -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: Hspice: Printing more than 132 cols -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] Re: [SI-LIST]EMI from two systems -
» [SI-LIST] [SI-LIST]EMI from two systems -
» [SI-LIST] Hspice: Printing more than 132 cols -
» [SI-LIST] Austin Area Job Opening -
» [SI-LIST] si/pd position available -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] R: Reply: Antwort: Re: Decoupling capacitors for BGA -
» [SI-LIST] Reply: Antwort: Re: Decoupling capacitors for BGA -
» [SI-LIST] Antwort: Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA - capacitor networks -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Web cast seminars -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Faraydon Pakbaz/Burlington/IBM is out of the office. -
» [SI-LIST] Re: Web cast seminars -
» [SI-LIST] Web cast seminars -
» [SI-LIST] Re: Decoupling capacitors for BGA -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Decoupling capacitors for BGA -
» [SI-LIST] Re: 8B10B encode/decode -
» [SI-LIST] Re: 8B10B encode/decode -
» [SI-LIST] Video System Engineer needed in Santa Clara, CA; -
» [SI-LIST] Re: OT: ??Encoded?? -
» [SI-LIST] Re: 8B10B encode/decode -
» [SI-LIST] Re: OT: ??Encoded?? -
» [SI-LIST] Re: 8B10B encode/decode -
» [SI-LIST] Re: 8B10B encode/decode -
» [SI-LIST] Re: OT: ??Encoded?? -
» [SI-LIST] OT: ??Encoded?? -
» [SI-LIST] 8B10B encode/decode -
» [SI-LIST] Re: 0.4mm pitch PBGA routing -
» [SI-LIST] Re: 0.4mm pitch PBGA routing -
» [SI-LIST] Re: Hspice: Look up tables -
» [SI-LIST] Microstrip Trace Under Nickel -
» [SI-LIST] 0.4mm pitch PBGA routing -
» [SI-LIST] Re: Hspice: Look up tables -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Re: Microstrip Trace under Nickel -
» [SI-LIST] Microstrip Trace under Nickel -
» [SI-LIST] Re: Hspice: Look up tables -
» [SI-LIST] Re: how to extract RLC values for package -
» [SI-LIST] Re: Hspice: Look up tables -
» [SI-LIST] Hspice: Look up tables -
» [SI-LIST] Re: Stackup Analysis Brain Storming -
» [SI-LIST] Stackup Analysis Brain Storming -
» [SI-LIST] SI and GHz Test - meeting in Santa Clara Valley -
» [SI-LIST] Signal Integrity Position Opening at Form Factor Inc. -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: how to extract RLC values for package -
» [SI-LIST] Job Posting -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: how to extract RLC values for package -
» [SI-LIST] how to extract RLC values for package -
» [SI-LIST] R: Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Meeting Announcement: IEEE-EMCS Santa Clara Valley Chapter, Tuesday May 9 -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Ethernet switch chip -
» [SI-LIST] Senior Engineering Technician, Andover MA. -
» [SI-LIST] Re: Ethernet switch chip -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Ethernet switch chip -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Signal Integrity Position Opening at Form Factor Inc. -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Routing Signals Between PWB Layers - Part 2 -
» [SI-LIST] Impedance Matching in SPICE -
» [SI-LIST] Impedance Matching in SPICE -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation) -
» [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation) -
» [SI-LIST] Re: Effects of solder layer on exposed traces -
» [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation) -