[SI-LIST] Re: Capacitors arrays. worth it or not?

  • From: "Hill, John" <jhill@xxxxxxxxxx>
  • To: "steve weir" <weirsi@xxxxxxxxxx>, <Mark.Randol@xxxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 22 May 2006 16:50:05 -0400

Steve,

I'm sorry to be a little thick on this issue, but I may be getting the
two orientations confused. If I understand you correctly, the following
is true:

It is Edie currents that keep the current concentrated in the lower
plates of a capacitor when the capacitor is mounted horizontally, which
we are defining as having the plates parallel to the board. This creates
a resonate cavity under the part.

When the capacitor is mounted with the plates perpendicular to the board
the current flows through all the plates.

Is this correct?

John


=20

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-----Original Message-----

From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
Sent: Monday, May 22, 2006 2:41 PM
To: Hill, John; Mark.Randol@xxxxxxxxxx; si-list
Subject: Re: [SI-LIST] Re: Capacitors arrays. worth it or not?

John, when the plates of a cap are parallel to the planes, eddy=20
currents block field penetration to the upper plates through the=20
cavity.  The field still goes around the terminal metalization.  This=20
makes a resonant cavity.

Steve.
At 10:50 AM 5/22/2006, Hill, John wrote:
>Mark,=3D20
>
>We have uploaded an application note from American Technical Ceramics
>concerning placing capacitors vertical and horizontal. The URL is:
>
>http://si-list.org/files/tech_files/ATC%20select_cap_wireless.pdf
>
>I have also sent an e-mail to the application engineer about the issue
>of eddy currents limiting the field. The data in the application note
>does not look like it supports the idea and I do not understand the
>physics.=3D20
>
>John
>
>
>=3D20
>
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legally =3D
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for =3D
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the =3D
>employee or agent responsible for delivery of this message to the =3D
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=3D
>information is prohibited and may be unlawful. When addressed to Takata
=3D
>customers or vendors, any information contained in this e-mail is =3D
>subject to the terms and conditions in the governing contract, if =3D
>applicable. If you have received this communication in error, please =
=3D
>immediately notify us by return e-mail, permanently delete any =3D
>electronic copies of this communication and destroy any paper copies.
>---------------------------------------
>-----Original Message-----
>
>From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Mark Randol
>Sent: Monday, May 22, 2006 10:33 AM
>To: si-list
>Subject: [SI-LIST] Re: Capacitors arrays. worth it or not?
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx=3D3D20
> > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Jerry Martinson
> >=3D3D20
> > I've always wondered how discrete cap performance is affected=3D3D20
> > if the caps plates are parallel with the underlying plane or=3D3D20
> > if they are perpendicular.  I'd think that having them rolled=3D3D20
> > 90 degrees
> > (perpendicular) might make them perform better in some=3D3D20
> > regions.  I wonder how this would extend to arrays and=3D3D20
> > whether arrays are configured rolled or not.  Does anyone=3D3D20
> > know? =3D3D20
>
>American Technical Ceramics (ATC) used to recommend 'vertical'
placement
>of their porcelain caps for just this reason.  I've seen it make
several
>100MHz's of difference in the measured resonance frequency.  That was
on
>a relatively thick 2 layer PCB, so on a board with a thinner component
>to ground layer spacing this could be more significant <guess>.  I
>didn't find it on their web site, but here is their link.
>
>http://www.atceramics.com/
>
>Now how much of this was due to plate coupling to the substrate, or
>reduced effective capacitance and inductance because of current
crowding
>towards the new 'bottom' of all the plates, beats me.  It seems to me
in
>the horizontal orientation, the upper plates would have slightly more
>inductance due to the greater loop area.  Which effect dominates,
>capacitance or inductance? =3D3D20
>
>The problem at the time was fixed, so we didn't investigate further.
>
>--
>Mark Randol, RF Evaluation & Application Engineer
>Not speaking for my company, etc
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