[SI-LIST] Re: Capacitors arrays? worth it or not?
- From: "jeanpierrepoulin" <JeanPierrePoulin@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 21 May 2006 17:05:08 -0000
Thanks Alan for the recommendations on a formal analysis...
It did seem - given the sub 1ns rise time - that this was required
even if the two parts are right close to one another... so I've been
trying to improve on my previous approach (i.e. follow ref design
and 'sprinkle a few more caps just in case' methodology) to a more
scientific approach...
Reading on the subject to improve the understanding and reach some
approximation to science, I have thus far adopted Lee Ritchey's
approach, added some theory from Dr. Howard Johnson and verified the
whole thing with an old Micron app note...
However, the 'excel spreadsheet' that resulted is surely not optimal
and could induce us in some errors...
Are there any tools / methodology you have seen in your travels that
can assist with capacitor selection for high-speed designs such as
ours?
Many thanks!
Jean-Pierre
--- In si-list@xxxxxxxxxxxxxxx, Alan Hilton-Nickel
<Alan.Hiltonnickel@...> wrote:
>
> Jean-Pierre,
>
> You have some analysis to do, both electrical and mechanical.
>
> Keep in mind that as the form factor of the capacitor gets
smaller, the
> interconnect inductance becomes more dominant. This means that the
> lowest-inductance caps should generally be closest to the point of
> consumption (the chip). This often means underneath the chip. The
arrays
> and the odd form-factor caps may simply not be placeable without
> eliminating power or ground vias, which at some point defeats the
> purpose of using low-inductance caps since it increases the
inductance
> of the power-plane connection.
>
> I've often seen the arrays and X2Y/LICCs used most effectively on
the
> package, not the board. The higher cost of the parts is a key
factor as
> well.
>
> Good luck with this.
>
> Alan
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