[SI-LIST] Re: is clock pair-to-clock pair matching required in DDR?
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <s.vijay@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 23 May 2006 11:13:39 -0700
Vijay,
In reading your email a little more closely I had a couple more =
comments.
The matching within a clock pair is definitely required. As Dan =
mantioned
CLK to CLK#mismatch can lead to VIX violations, where WIX is the DC =
level of the
crossing point.
Also, it soulds like you were working to match DQS to CLK length at each =
SDRAM.
Its good to match your DQS to a narrowe range around CLK, but the =
sequence is as
follows.
Match all CLKs to a single length. Then match all DQS to a length =
window
around CLK. The controller usually has DLLs or some such thing which =
allows you
to have a fixed length offset between CLK and DQS, but the tighter the =
range of
byte lane lengths the betetr you can optimize timing. =20
Brian P. Moran
Intel Corporation=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Dan Bostan
Sent: Tuesday, May 23, 2006 8:07 AM
To: s.vijay@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: is clock pair-to-clock pair matching required in =
DDR?
Vijay,
How do you think the DQS is registered?
Of course there is a time relationship between the clock and DQS, thus =
DQ.
It is important to follow the layout rules for the clock, too.
Besides, if there is skew between the members of the clock, the crossing =
point may be outside of the spec, and certainly the duty cycle is not =
optimal.
Overall, the clock matching is important.
/dan
Vijay Sivasubramanian <s.vijay@xxxxxxxxxxxxx> wrote: Guys --
=20
We have designed a board with a Freescale powerQUICC processor. It has =
6 separate DDR clock outputs. We have 5 DDR on-board chips. My =
question is - do we have to match the length of each of the 5 =
clock-pairs? I don't quite understand the need for matching the =
individual clocks, but this was given in one of the Freescale app notes. =
The app note recommends 20mils matching within each of the clock pairs. =
=20
We have matched the individual clock pair w.r.t the corresponding DQS =
within 20mils and DQS to corresponding clock within 250mils. I feel as =
long as the Clock-DQS-Data relationship is maintained, the clock =
pair-to-pair matching might not be required. Would greatly appreciate =
your help on this.
=20
Thanks
Vijay
GDA Technologies Ltd.,
India
www.gdatech.com
=20
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