[SI-LIST] Re: AC coupling Capacitor

Scott,

I would think that value tolerance between the two independent
capacitors would lead to phase differences between the two signals.
Would a Capacitor array be a better selection?

John


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-----Original Message-----

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Friday, May 26, 2006 12:57 AM
To: Cortex.Chen@xxxxxxxxxxxx
Cc: pchauhan@xxxxxxxxxxx; istvan.novak@xxxxxxxxxxx;
jain.nitin@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AC coupling Capacitor

A DC blocking capacitor is a fairly large discontinuity in most systems,
unless care is taken in it's selection and board layout. Asking whether
the capacitor should be near the Tx or Rx side is the wrong question.
The question to ask is how the discontinuity of the capacitor interacts
with other discontinuities, and whether that will change your total
insertion loss and phase response across the data bandwidth.
I'm not going to give anyone the answer here, but looking at return loss
of all the cascaded elements of the interconnect is the key. Insertion
loss of individual elements is meaningless in the overall scheme of
things. We can compensate for insertion loss with equalization. But
phase shift is a different beast altogether.

regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

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Teraspeed Consulting Group LLC



Cortex.Chen@xxxxxxxxxxxx wrote:
> Hello Prakash,
>
> I also encountered your question about two years ago (when I
researched =3D
> Intel Bensley platform...).
> I tried to ask any contact windows from Intel, however, there is not
any =3D
> response and therefore I turned to review PCI-E interface.
> I like to share private thinking for your reference.
>
> Based on ac capacitor's functionality, there is not any difference =3D
> between transmitter and receiver.
> So the capacitors may theoretically be placed anywhere along the =3D
> interconnect...     =3D20
>
> In addition, we should meet both spec. of TX and Rx for PCI-E not only
=3D
> meets receiver's spec for post interface.
> If you have PCI-E spec (rev. 1.1) or/and NOTE1*, please open section =
=3D
> 4.3.3.4 and check the fig. 4-25 (transmitter test load).
> You could realize why the ac cap is closer to the transmitter for
PCI-E.
>
> Note1: PCI Express* Simulations: Differences between Pin and Pad =3D
> Measurements
>
> In addition, I am also searching some papers to discuss ac cap
location =3D
> for gain for SAS interface.
> You could check it....
>
> Regards,
>
> Cortex
>
> From: "Chauhan, Prakash" <pchauhan@xxxxxxxxxxx>
> Date: Thu May 25 08:37:01 CDT 2006
> To: istvan.novak@xxxxxxxxxxx, jain.nitin@xxxxxxxxx, =3D
> si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: AC coupling Capacitor
>
> Hi Istvan,
>       I have seen design guides that suggest that for Ethernet (Gig-E
> and Xaui) the caps should be close to the receiving end while for PCI
> express these should be closer to the transmit side (4.75 inch max
> suggested in both cases).  Both these are 8B/10B encoded, 100 ohm
> differential, serial links and it is not clear to me why this should
be
> different for these two serial interfaces (given that the PCB loss and
> impedance discontinuity due to the caps should affect both types of
> links in very similar manner).  Perhaps it has something to do with
the
> preemphasis and receive equalization characteristics of the
> driver/receiver?! =3D3D20
>
> --Prakash.   =3D3D20
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of istvan.novak@xxxxxxxxxxx
> Sent: Thursday, May 25, 2006 8:10 AM
> To: jain.nitin@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: AC coupling Capacitor
>
> Nitin,
>
> Regular surface-mount DC-blocking capacitors will create
discontinuities
> in the differential lines, because most of our traces today are much
> narrower than the capacitor pad and body.  The typically strongest
> discontinuity is the parallel body capacitance to ground.  If you use
> two capacitors along eachline, you get two discontinuities, so do it
> only if there is a strong reason. =3D3D20
>
> Regarding their location along the lines: as a first-cut approach,
their
> location should not (and does not) matter, you just want to place the
> capacitors on both lines at the same location symmetrically so that
mode
> conversion is minimized.  If you (have to) take a closer look, the
> location of the discontinuity along the line may matters somewhat as
it
> interacts with the losses and non-ideal impedances of the lines and
> transmit/receive impedances.  If this matters, you need a simulator to
> find the answer.
>
> Regards,
>
> Istvan Novak
> SUN Microsystems
>
> From: jain.nitin@xxxxxxxxx
> Date: Thu May 25 06:03:58 CDT 2006
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] AC coupling Capacitor
>
>
>  Hello,
>
> For a gigabit differential pair AC coupling capacitor is used. But
what
> exactly is the use of AC coupling capacitors? I believe that they are
> used when the bias voltage of driver & receiver are =
different.=3D3D3D0D
>
> Also where exactly AC coupling capacitors should be placed when the
> differential trace is running on a backplane from one daughter card to
> other (at driver end or at receiver end).
>
> What will happen if two AC coupling caps are used. One at driver side
> and other at receiver side.
>
> With regards,
> Nitin
>
>
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