Posts for si-list, 06-2006

Browse: Last Month: 05-2006 Main Archive Page Next Month: 07-2006

» [SI-LIST] Re: Trace Spacing Rule -
» [SI-LIST] Re: Fibre channel interconnect margins -
» [SI-LIST] Fibre channel interconnect margins -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Advantages of Pi termination network -
» [SI-LIST] Advantages of Pi termination network -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Mixed-mode impedance matrix -
» [SI-LIST] Re: Trace Spacing Rule -
» [SI-LIST] Re: Trace Spacing Rule -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Mixed-mode impedance matrix -
» [SI-LIST] Re: Trace Spacing Rule -
» [SI-LIST] Re: spice question -
» [SI-LIST] Re: DDR-2 memory models -
» [SI-LIST] Re: PCB Reverse Engineering -
» [SI-LIST] Re: Trace Spacing Rule -
» [SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package -
» [SI-LIST] Trace Spacing Rule -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] DDR-2 memory models -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: how to model the via in Sigexplorer610 -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Book -
» [SI-LIST] spice question -
» [SI-LIST] Re: Feedback on graphic image -
» [SI-LIST] Re: sin(x)/x interpolation -
» [SI-LIST] Re: sin(x)/x interpolation -
» [SI-LIST] Re: Feedback on graphic image -
» [SI-LIST] Re: Feedback on graphic image -
» [SI-LIST] Altera Netseminar on Singal Integrity, June 28 -
» [SI-LIST] Re: how to model the via in Sigexplorer610 -
» [SI-LIST] FW: SI Employment Opportunity at Altera: Posting -
» [SI-LIST] Re: Decoupling Capacitor ESR/ESL -
» [SI-LIST] Feedback on graphic image -
» [SI-LIST] Decoupling Capacitor ESR/ESL -
» [SI-LIST] Re: DAC clock -
» [SI-LIST] Re: sin(x)/x interpolation -
» [SI-LIST] DAC clock -
» [SI-LIST] Re: sin(x)/x interpolation -
» [SI-LIST] sin(x)/x interpolation -
» [SI-LIST] how to model the via in Sigexplorer610 -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Signal Integrity Opening with Force10 Networks -
» [SI-LIST] SI openning at Marvell -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: cat 6 RJ45 jack for PCB -
» [SI-LIST] Re: Rocket I/O models for hspice -
» [SI-LIST] Rocket I/O models for hspice -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Digital PI/SI and RF SI/PI -
» [SI-LIST] Re: Mictor Connectors -
» [SI-LIST] Re: Twisting of differential pair traces -
» [SI-LIST] Re: cat 6 RJ45 jack for PCB -
» [SI-LIST] Re: cat 6 RJ45 jack for PCB -
» [SI-LIST] Re: Mictor Connectors -
» [SI-LIST] Re: Mictor Connectors -
» [SI-LIST] Re: cat 6 RJ45 jack for PCB -
» [SI-LIST] Re: cat 6 RJ45 jack for PCB -
» [SI-LIST] cat 6 RJ45 jack for PCB -
» [SI-LIST] Re: What is imporatnt in a simulator? -
» [SI-LIST] Re: What is imporatnt in a simulator? -
» [SI-LIST] Re: What is important in a simulator? -
» [SI-LIST] Re: What is imporatnt in a simulator? -
» [SI-LIST] SI-related jobs at Sigrity -
» [SI-LIST] What is imporatnt in a simulator? -
» [SI-LIST] Re: Twisting of differential pair traces -
» [SI-LIST] Twisting of differential pair traces -
» [SI-LIST] Mictor Connectors -
» [SI-LIST] Job Opening: IC Package Electrical Simulation & Modeling Engineer -
» [SI-LIST] Re: Shielding Question -
» [SI-LIST] 回复： RE: 回复： Re: 14 Layer Stackup -
» [SI-LIST] Re: Signal Integrity and PCB layout positions for Cisco R&D center in CHINA (Shanghai, China) -
» [SI-LIST] Re: Shielding Question -
» [SI-LIST] Re: Shielding Question -
» [SI-LIST] Re: »Ø¸´£º Re: 14 Layer Stackup -
» [SI-LIST] Re: 14 Layer Stackup -
» [SI-LIST] Re: 14 Layer Stackup -
» [SI-LIST] Shielding Question -
» [SI-LIST] Re: Undershoot or Overshoot Issue at Die Level -
» [SI-LIST] Undershoot or Overshoot Issue at Die Level -
» [SI-LIST] Strange non-monotonic edge after LVPECL and LVDS interface circuit -
» [SI-LIST] 回复： Re: 14 Layer Stackup -
» [SI-LIST] Signal integrity position available at Hewlett Packard in Richardson, Texas -
» [SI-LIST] Re: PCI Bus -
» [SI-LIST] Re: 14 Layer Stackup -
» [SI-LIST] Re: 14 Layer Stackup -
» [SI-LIST] Re: 14 Layer Stackup -
» [SI-LIST] Re: 14 Layer Stackup -
» [SI-LIST] Signal Integrity and PCB layout positions for Cisco R&D center in CHINA (Shanghai, China) -
» [SI-LIST] 14 Layer Stackup -
» [SI-LIST] Re: PCI Bus -
» [SI-LIST] Re: PCI Bus -
» [SI-LIST] Re: PCI Bus -
» [SI-LIST] Re: SDR SDRAM Layout -
» [SI-LIST] Re: PCI Bus -
» [SI-LIST] SDR SDRAM Layout -
» [SI-LIST] PCI Bus -
» [SI-LIST] Re: 8 bit async. parallel bus on back plane -
» [SI-LIST] Re: 8 bit async. parallel bus on back plane -
» [SI-LIST] Re: EMI -
» [SI-LIST] Re: How to get Intel IBIS models -
» [SI-LIST] Re: 8 bit async. parallel bus on back plane -
» [SI-LIST] Re: 8 bit async. parallel bus on back plane -
» [SI-LIST] Re: R: CPW -
» [SI-LIST] 8 bit async. parallel bus on back plane -
» [SI-LIST] Signal Integrity project in San Jose, CA -
» [SI-LIST] Re: How to get Intel IBIS models -
» [SI-LIST] How to get Intel IBIS models -
» [SI-LIST] Re: EMI -
» [SI-LIST] R: CPW -
» [SI-LIST] Re: CPW -
» [SI-LIST] Re: CPW -
» [SI-LIST] Re: CPW -
» [SI-LIST] Re: CPW -
» [SI-LIST] Re: CPW -
» [SI-LIST] Re: EMI -
» [SI-LIST] CPW -
» [SI-LIST] Re: EMI -
» [SI-LIST] Re: EMI -
» [SI-LIST] EMI -
» [SI-LIST] Re: Pre-emphasis Vs De-emphasis -
» [SI-LIST] Re: Setup-Hold time -
» [SI-LIST] Re: simulating connectors in HyperLynx -
» [SI-LIST] Re: Pre-emphasis Vs De-emphasis -
» [SI-LIST] Re: Pre-emphasis Vs De-emphasis -
» [SI-LIST] Pre-emphasis Vs De-emphasis -
» [SI-LIST] Re: Inter-plane capacitance -
» [SI-LIST] Re: Inter-plane capacitance -
» [SI-LIST] Re: slow down the edges -
» [SI-LIST] Re: simulating connectors in Hyperlynx -
» [SI-LIST] Re: simulating connectors in Hyperlynx -
» [SI-LIST] Re: Inter-plane capacitance -
» [SI-LIST] simulating connectors in Hyperlynx -
» [SI-LIST] Re: Value of pull up resistors -
» [SI-LIST] R: Inter-plane capacitance -
» [SI-LIST] Simulation models for Agilent 81250 ParBERT drivers -
» [SI-LIST] Re: Inter-plane capacitance -
» [SI-LIST] Inter-plane capacitance -
» [SI-LIST] Re: Setup-Hold time -
» [SI-LIST] Re: about component modeling solution -
» [SI-LIST] slow down the edges -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Digilog design and tesla coils -
» [SI-LIST] Re: Value of pull up resistors -
» [SI-LIST] Re: Value of pull up resistors -
» [SI-LIST] Value of pull up resistors -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] Re: S-parameter passivity... Interpreting the results. -
» [SI-LIST] S-parameter passivity... Interpreting the results. -
» [SI-LIST] Setup-Hold time -
» [SI-LIST] about component modeling solution -
» [SI-LIST] Re: Signal Integrity issues at -40 degrees C -
» [SI-LIST] FW: CIE/EPMC announcement - Dinner Seminar on 6/28 -
» [SI-LIST] Doug Unplugged! -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: RJ-45 Connector -
» [SI-LIST] Re: Modelling radiation -
» [SI-LIST] Modelling radiation -
» [SI-LIST] Re: Timing Analysis -
» [SI-LIST] Timing Analysis -
» [SI-LIST] RJ-45 Connector -
» [SI-LIST] Senior/lead SI engineer position @ Cisco San Jose -
» [SI-LIST] R: Package characterization -
» [SI-LIST] Re: SDRAM Termination -
» [SI-LIST] Re: SDRAM Termination -
» [SI-LIST] Package characterisation -
» [SI-LIST] Re: Split GND Plane on PKG -
» [SI-LIST] Package characterization -
» [SI-LIST] analog - digtal power -
» [SI-LIST] Re: SDRAM Termination -
» [SI-LIST] Re: Split GND Plane on PKG -
» [SI-LIST] Re: About Touchstone file -
» [SI-LIST] Re: Long trace open on the both ends -
» [SI-LIST] Re: Power/GND and fires -
» [SI-LIST] Re: Long trace open on the both ends -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: SDRAM Termination -
» [SI-LIST] 回复： Re: SDRAM Termination -
» [SI-LIST] Re: SDRAM Termination -
» [SI-LIST] SDRAM Termination -
» [SI-LIST] Re: Long trace open on the both ends -
» [SI-LIST] Split GND Plane on PKG -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] About Touchstone file -
» [SI-LIST] Re: Power/GND and fires -
» [SI-LIST] Power/GND and fires -
» [SI-LIST] Long trace open on the both ends -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: What is the difference between ANA and VNA? -
» [SI-LIST] Re: SPLIT POWER PLANE -
» [SI-LIST] Re: SPLIT POWER PLANE -
» [SI-LIST] SPLIT POWER PLANE -
» [SI-LIST] Re: :Is mini PCI and PCI are compatable to interface with each other -
» [SI-LIST] AW: How can mentor Boardstation interface with Ansoft SI-Wave ? -
» [SI-LIST] Signal Integrity Position @ PMC-Sierra -
» [SI-LIST] Job Opening - PHY Applications Engineer @ Broadcom -
» [SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package -
» [SI-LIST] Re: SI-List Graphics or pics -
» [SI-LIST] Re: SI-List Graphics or pics -
» [SI-LIST] Re: Recall: SI-List Graphics or pics -
» [SI-LIST] Recall: SI-List Graphics or pics -
» [SI-LIST] Recall: SI-List Graphics or pics -
» [SI-LIST] SI-List Graphics or pics -
» [SI-LIST] Re: AC coupling Capacitor (Eye Diagram Issue) -
» [SI-LIST] Re: AC coupling Capacitor (Eye Diagram Issue) -
» [SI-LIST] Re: How can mentor Boardstation interface with Ansoft SI-Wave ? -
» [SI-LIST] Reg: Buffer fanout -
» [SI-LIST] Measuring structural resonances for fun and relaxation (and work too) -
» [SI-LIST] What is the difference between ANA and VNA? -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] How can mentor Boardstation interface with Ansoft SI-Wave ? -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: Running analog video on micro-coaxH -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: PCI-X (133Mhz) bus terminations -
» [SI-LIST] Dallas EMC Colloquium -- July 13, 2006 -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: gigabit ethernet trace length -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: PCI-X (133Mhz) bus terminations -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: [SPAM] Re: Question about split gnd planes -
» [SI-LIST] Re: Question about split gnd planes -
» [SI-LIST] Re: Copper balancing -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Copper balancing/ The process is called THIEVING -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Strange resets happening in one of our circuit boards -
» [SI-LIST] Strange resets happening in one of our circuit boards -
» [SI-LIST] Re: Running analog video on micro-coax -
» [SI-LIST] Running analog video on micro-coax -
» [SI-LIST] Re: PCI-X (133Mhz) bus terminations -
» [SI-LIST] Re: SSN can affect input behaviour? -
» [SI-LIST] SSN can affect input behaviour? -
» [SI-LIST] Re: PCI-X (133Mhz) bus terminations -