[SI-LIST] help
- From: "Narasimhan, Sarath (Sarath)" <sarath@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 23 May 2006 17:52:44 -0400
I'm searching for an accurate highspeed design model of vias traces
bends routes over split planes in HSPICE. I'm trying to do pre-layout
simulations of high speed signals reaching 10G.Is what I'm trying to
do correct or do I need a tool like Ansoft. Is anyone aware of any
open source high speed design tool that runs on Linux or Unix.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: Tuesday, May 23, 2006 4:34 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: is clock pair-to-clock pair matching required in
DDR?
In the read path when you cross a 2x speed DDR path to the 1x common =
clock boundary, you inheritedly have to have a least an elastic buffer =
of one transfer cycle. Since the capture of the data is guarantee by the =
DQ/DQS relationship, the difference (not the absolute value) of DQS =
dealy (hence clock length) just need to fit within a transfer cycle. =
That's a huge tolerance for a point to point net length. I still don't =
understand why you need to match clock/DQS lengths between DQS/Clock =
groups with tight tolerance, especially with a point to point topology =
as stated.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Peterson, James F
(FL51)
Sent: Tuesday, May 23, 2006 11:15 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: is clock pair-to-clock pair matching required in
DDR?
=3D20
yes, for our DDR SDRAM design it was necessary (note: ours did not
include a Freescale processor). The key to understanding why, is in
understanding the timing details of the interface...on a read cycle you
have to cross a clock domain back into the controller and you don't
really want 5 different answers for that timing. "so, I'll match the
DQS", (you might say), but you can't match DQS's unless you match the
source of a read DQS - which is CK and CKn....
jim=3D20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Vijay Sivasubramanian
Sent: Tuesday, May 23, 2006 7:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] is clock pair-to-clock pair matching required in DDR?
Guys --
=3D20
We have designed a board with a Freescale powerQUICC processor. It has
6 separate DDR clock outputs. We have 5 DDR on-board chips. My
question is - do we have to match the length of each of the 5
clock-pairs? I don't quite understand the need for matching the
individual clocks, but this was given in one of the Freescale app notes.
The app note recommends 20mils matching within each of the clock pairs.
We have matched the individual clock pair w.r.t the corresponding DQS
within 20mils and DQS to corresponding clock within 250mils. I feel as
long as the Clock-DQS-Data relationship is maintained, the clock
pair-to-pair matching might not be required. Would greatly appreciate
your help on this.
=3D20
Thanks
Vijay
GDA Technologies Ltd.,
India
www.gdatech.com
=3D20
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=3D20
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