[SI-LIST] Re: PCB stackup

  • From: "Ahmed Mubeen-W17666" <Mubeen.Ahmed@xxxxxxxxxxxx>
  • To: <leeritchey@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 23 May 2006 17:26:51 -0400

On a PCB with so many Power Planes How would it be possible to have so
many planes with limited pcb layers.
If board space is a problem would it be advisable to run traces with
different voltage levels under different power planes?

Power planes are no doubt a better idea but we current PCB technology it
would cost a lot to create embedded capacitor (ZICORE Tech).


-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]=20
Sent: Tuesday, May 23, 2006 3:52 PM
To: Ahmed Mubeen-W17666; lnima@xxxxxxxxxx; s_aout@xxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: PCB stackup=20

First commnet- not necessarily so about planes and EMI.

Routing power with thick traces for high speed designs is not a good
idea.=20
Might work for TTL.  But TTL is gone.=20


> [Original Message]
> From: Ahmed Mubeen-W17666 <Mubeen.Ahmed@xxxxxxxxxxxx>
> To: <lnima@xxxxxxxxxx>; <s_aout@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 5/23/2006 1:06:43 PM
> Subject: [SI-LIST] Re: PCB stackup
>
> Have some many power planes may hurt rather than helping. Having so=20
> many power planes would give return current paths to signals that are=20
> of different voltage level. This causes more EMI since you end up=20
> crossing moats.
>
> Also, do not want to have two different power fills on top of each=20
> other.
>
> It is better to calculate the total current needed by certain IC and=20
> run thick traces (according to calculation) isolated from Clocks.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Nima Lotfi
> Sent: Tuesday, May 23, 2006 12:31 PM
> To: s_aout@xxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: PCB stackup=3D20
>
> To minimize your radiation you may want to=3D3D20
>
> 1) ensure you have a low impedance power plane
>
> 2) be careful about shielding any cable grounds to your faraday =3D=20
> case=3D3D20 "gnd".
>
> To get a low impedance power plane you may want to consider having=20
> full planes power planes, and a good decoupling strategy.
>
> Also separation of ground plane to power plane plays a major role in=20
> reducing power plane impedance.  Use the minimum prepreg size that can

> be supported for volume production.
>
> As for cables that is a whole different story and I don't think it is=20
> relevant to your situation.
>
> Nima Lotfi
>
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > Sent: Monday, February 21, 2005 3:03 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] PCB stackup
> >=3D3D20
> >=3D3D20
> > Hi all,
> >=3D3D20
> > I am working on a product which requires high shielding (no =3D20=20
> >interference with mobile pagers) and the PCB goes in plastic =20
> >enclosure
>
> >(w/o metallic paint).  The highest working frequency is  200Mhz and=20
> >the
>
> >PCB stackup is :
> >=3D3D20
> > TOP    ground
> > Layer1 signal + power fill 1.8V
> > Layer2 ground
> > Layer3 signal + power fill 3.3V
> > Layer 4 signal + power fill 5V
> > Layer 5 ground
> > Layer 6 signal + power fill 3.3V
> > Bottom ground
> >=3D3D20
> >=3D3D20
> > Is this stackup ok? and do you think that not having a full power=20
> >=3D20 plane would be a problem?
> >=3D3D20
> >=3D3D20
> > thanks
> >=3D3D20
> >=3D3D20
> >=3D3D20
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