Posts for si-list, 04-2006

Browse: Last Month: 03-2006 Main Archive Page Next Month: 05-2006

» [SI-LIST] Effects of solder layer on exposed traces -
» [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation) -
» [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation) -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] E-mail address harvesting (WAS; Re: Signal integrity and simulation) -
» [SI-LIST] Re: Design For Manufacturing assessment Tools for PCB Designs -
» [SI-LIST] Re: Design For Manufacturing assessment Tools for PCB Designs -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Design For Manufacturing assessment Tools for PCB Designs -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Design For Manufacturing assessment Tools for PCB Designs -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Design For Manufacturing assessment Tools for PCB Designs -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Design For Manufacturing assessment Tools for PCB Designs -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Re: Maximum Current -
» [SI-LIST] Maximum Current -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Analog/Digital vss connection for a PLL IC -
» [SI-LIST] Analog/Digital vss connection for a PLL IC -
» [SI-LIST] Re: Non monotonicity in daisy chain topology -
» [SI-LIST] Non monotonicity in daisy chain topology -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Re: FPGA SI Issues in Space Applications -
» [SI-LIST] Job openings at CST of America -
» [SI-LIST] R: Re: Engineering Effort vs. Time -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] PI for analog device -
» [SI-LIST] FPGA SI Issues in Space Applications -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Job Opening at Altera -
» [SI-LIST] Job Opening at Altera -
» [SI-LIST] Re: Engineering Effort vs. Time -
» [SI-LIST] Re: Engineering Effort vs. Time -
» [SI-LIST] Engineering Effort vs. Time -
» [SI-LIST] Re: Session of interest to SI engineers at DesignCon 2006 -
» [SI-LIST] Re: Session of interest to SI engineers at DesignCon 2006 -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Copper Pours -
» [SI-LIST] DDR2 DQS Question -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Board Design Lead Position Available at San Jose Company (perm/fulltime) -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Copper Pours -
» [SI-LIST] Re: Copper Pours -
» [SI-LIST] Re: Analysis about hot-plug -
» [SI-LIST] Re: Analysis about hot-plug -
» [SI-LIST] Analysis about hot-plug -
» [SI-LIST] Re: Session of interest to SI engineers at DesignCon 2006 -
» [SI-LIST] LVDS spacewire shield grounding -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Differential pair Impedance - Q on test data -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop, clarification -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Session of interest to SI engineers at DesignCon 2006 -
» [SI-LIST] Re: Question regarding current loop -
» [SI-LIST] Re: Question regarding current loop, clarification -
» [SI-LIST] Re: Differential pair Impedance - Q on test data -
» [SI-LIST] Question regarding current loop -
» [SI-LIST] Re: Differential pair Impedance - Q on test data -
» [SI-LIST] Differential pair Impedance - Q on test data -
» [SI-LIST] Re: differential pair routing topology -
» [SI-LIST] Re: differential pair routing topology -
» [SI-LIST] separation of analog and digital ground on a package -
» [SI-LIST] Re: differential pair routing topology -
» [SI-LIST] Re: Copper Pours -
» [SI-LIST] Inductance puzzle -
» [SI-LIST] Re: differential pair routing topology -
» [SI-LIST] Re: varactor diode in clock delays -
» [SI-LIST] Re: Copper Pours -
» [SI-LIST] varactor diode in clock delays -
» [SI-LIST] Re: Sr. Researcher on High-speed Interconnect Position Opening in Huawei(updated) -
» [SI-LIST] SUBSCRIBE, -
» [SI-LIST] Inductance puzzle -
» [SI-LIST] Re: Ceramic Vs Tantalum for bulk bypassing -
» [SI-LIST] Copper Pours -
» [SI-LIST] Two SI application engineer positions open in Altera, San Jose. -
» [SI-LIST] Re: Question regarding return current in a differentialpair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] differential pair routing topology -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Ceramic Vs Tantalum for bulk bypassing -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Ceramic Vs Tantalum for bulk bypassing -
» [SI-LIST] Sr. Researcher on High-speed Interconnect Position Opening in Huawei -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Re: Question regarding return current in a differential pair -
» [SI-LIST] Question regarding return current in a differential pair -
» [SI-LIST] Re: impedance calculation -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: About the DDR2 Data Tim ing Budget Calculation -
» [SI-LIST] impedance calculation -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: About the DDR2 Data Tim ing Budget Calculation -
» [SI-LIST] Re: About the DDR2 Data Timing Budget Calculation -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: About the DDR2 Data Timing Budget Calculation -
» [SI-LIST] Patrick C Herbert/Cleveland/RA/Rockwell is out of the office. -
» [SI-LIST] Re: About the DDR2 Data Timing Budget Calculation -
» [SI-LIST] About the DDR2 Data Timing Budget Calculation -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: Free Engineering Calculators -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Free Engineering Calculators -
» [SI-LIST] Re: Impedance control with split ground planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Impedance control with split ground planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] Re: 4-Port VNA calibration question -
» [SI-LIST] 4-Port VNA calibration question -
» [SI-LIST] Re: Rogers4003 Board Characterization -
» [SI-LIST] Re: Return path for stripline between two power planes -
» [SI-LIST] Return path for stripline between two power planes -
» [SI-LIST] Re: R: Rogers4003 Board Characterization -
» [SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability -
» [SI-LIST] Re: Rogers4003 Board Characterization -
» [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: TDR measurement -
» [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: TDR measurement -
» [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: TDR measurement -
» [SI-LIST] How do two Random (Gaussian) Jitter specs add? -
» [SI-LIST] Re: R: Rogers4003 Board Characterization -
» [SI-LIST] TDR measurement -
» [SI-LIST] R: Rogers4003 Board Characterization -
» [SI-LIST] Re: Rogers4003 Board Characterization -
» [SI-LIST] Re: Rogers4003 Board Characterization -
» [SI-LIST] Re: Rogers4003 Board Characterization -
» [SI-LIST] Re: [SPAM] Rogers4003 Board Characterization -
» [SI-LIST] Re: Ferrite bead question - Downloadable presentation -
» [SI-LIST] Rogers4003 Board Characterization -
» [SI-LIST] Re: IC Corners and Etch Corners -
» [SI-LIST] Miller Coefficient Factor (MCF) -
» [SI-LIST] IC Corners and Etch Corners -
» [SI-LIST] Re: Ferrite bead question - Downloadable presentation -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Ferrite bead question - Downloadable presentation -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Check it out -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Check it out -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] SPI 2006 - Call For Participation: Program now available -
» [SI-LIST] Re: SSTL2 classI without RS and RT on short length -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: DDR2 design -
» [SI-LIST] Re: Tradeoffs of split power plane vs. multiple power layers.... -
» [SI-LIST] Re: Ferrite bead question -
» [SI-LIST] Re: Power Integrity measurement equipment -
» [SI-LIST] Re: SSTL2 classI without RS and RT on short length -
» [SI-LIST] Re: SSTL2 classI without RS and RT on short length -
» [SI-LIST] Ferrite bead question -
» [SI-LIST] DDR2 SDRAM speed bins -
» [SI-LIST] Re: Power Integrity measurement equipment -
» [SI-LIST] Re: SSTL2 classI without RS and RT on short length -
» [SI-LIST] Re: SSTL2 classI without RS and RT on short length -
» [SI-LIST] Re: SSTL2 classI without RS and RT on short length -
» [SI-LIST] SSTL2 classI without RS and RT on short length -
» [SI-LIST] Re: Query about VIA modeling -
» [SI-LIST] Re: Routing Signals Between PWB Layers -
» [SI-LIST] Query about VIA modeling -
» [SI-LIST] Re: Power Integrity measurement equipment -
» [SI-LIST] Re: Input Impedance Changing -
» [SI-LIST] Re: Input Impedance Changing -
» [SI-LIST] R: Input Impedance Changing -
» [SI-LIST] Input Impedance Changing -
» [SI-LIST] Routing Signals Between PWB Layers -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters -
» [SI-LIST] Re: Power Integrity measurement equipment -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters -
» [SI-LIST] Testing again -
» [SI-LIST] Re: Tradeoffs of split power plane vs. multiple power layers.... -
» [SI-LIST] commands -
» [SI-LIST] HELP -
» [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E -
» [SI-LIST] Tradeoffs of split power plane vs. multiple power layers.... -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters -
» [SI-LIST] EM Modeling Position at Freescale Semiconductor Inc. -
» [SI-LIST] Re: Ethernet magnetics question -
» [SI-LIST] Re: Ethernet magnetics question -
» [SI-LIST] EM Modeling Position at Freescale Semiconductor Inc. [Tempe AZ] -
» [SI-LIST] Cisco Systems - Signal Integrity opening in San Jose, CA -
» [SI-LIST] Re: Ethernet magnetics question -
» [SI-LIST] Re: Ethernet magnetics question -
» [SI-LIST] Ethernet magnetics question -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa's larger than 8 characters -
» [SI-LIST] FW: Re: Theory v. practice, following Re: DesignCon quote -
» [SI-LIST] EM Modeling Position at Freescale Semiconductor Inc. -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa's larger than 8 characters -
» [SI-LIST] Re: Getting Hspice to accept numbers with mantissa's larger than 8 characters -
» [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E -
» [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E -
» [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E -
» [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E -
» [SI-LIST] How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E -
» [SI-LIST] Getting Hspice to accept numbers with mantissa's larger than 8 characters -
» [SI-LIST] Re: Cumulative probability (BER) vs sigma value of normal distribution -
» [SI-LIST] Cumulative probability (BER) vs sigma value of normal distributio n -
» [SI-LIST] Signal Integrity Lead Position Available in San Jose, CA (perm/fulltime) -
» [SI-LIST] Testing -
» [SI-LIST] Future Directions in IC and Package Design Workshop, FDIP'06 -
» [SI-LIST] Re: Theory v. practice, following Re: DesignCon quote -
» [SI-LIST] Re: Theory v. practice, following Re: DesignCon quote -
» [SI-LIST] Re: Theory v. practice, following Re: DesignCon quote -
» [SI-LIST] Re: Theory v. practice, following Re: DesignCon quote -
» [SI-LIST] H.264 Video Compression Asic Design, new Yahoo group; -
» [SI-LIST] H.264 Video Compression Asic Design, new Yahoo group; -
» [SI-LIST] Re: How to simulate length mismatch of PCB traces -