[SI-LIST] Re: Capacitors arrays. worth it or not?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Larry Smith" <LSMITH@xxxxxxxxxx>,"Hill, John" <jhill@xxxxxxxxxx>, <Mark.Randol@xxxxxxxxxx>,"si-list" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 23 May 2006 10:10:25 -0700
Larry, I am familiar with the excellent models that you have
developed as well as Istvan's papers. We have some cool CST
simulations on this. For most of the caps that I play with I have
found that a three branch model correlates measured common geometry
mounts within a half dB from DC out to a couple of GHz. The number
of branches needed depends on just how close the cap gets to the planes.
Best Regards,
Steve.
At 09:46 AM 5/23/2006, Larry Smith wrote:
>Steve, John - here is another interesting way to look at it. When a
>ceramic capacitor is mounted such that the capacitor plates are parallel
>to the PCB plates, the capacitor forms a vertical transmission line with
>inductance per unit length and capacitance per unit length. The far end
>of the transmission line is open circuit (air) and the near end is
>nearly shorted (PCB power planes present a very low impedance to the
>mounted capacitor). This makes a quarter wavelength resonator similar
>to a 50 Ohm transmission line that is open on one end. At the quarter
>wavelength frequency, the open circuit at the far end becomes a low
>impedance node at the near end. This is the series resonant frequency
>of the capacitor. The peaks and dips that you might see beyond the
>series resonance of the capacitor are associated with the half, 3/4,
>full, 1 1/4, etc, wavelengths of the capacitor transmission line.
>
>To see this effect, you must mount the capacitor on vias and pads that
>have less inductance than the capacitor itself otherwise the resonance
>is completely dominated by the mounting inductance. Tall capacitors
>with very low ESR show this effect the best. I was evaluating a bunch
>of capacitors one time and the 33nF NPO 2220 size capacitor strongly
>exhibited these properties. It is very tall and has low ESR because of
>the many, many plates. I had it mounted on a fixture estimated at 83pH
>but the inductance associated with the capacitor itself was about 1 nH.
>There were perhaps a half a dozen dips and peaks beyond series resonance
>associated with the transmission line properties of the capacitor.
>
>David Hockanson and I did a couple of papers on this at 2002 and 2003
>ECTC conference and another one at 2005 Design Con. You can actually
>use the transmission line properties of a capacitor to develop a ladder
>SPICE model and extract the element values. The model accurately
>predicts the reduction of inductance and the increase in ESR of a
>capacitor mounted on low inductance pads. This is important to simulate
>the parallel resonance that may occur between two capacitors or between
>a capacitor and power planes. Ceramic capacitors have a lot more ESR
>and less ESL than might be expected from a simple RLC model beyond
>series resonance.
>
>Mounting capacitors with the plates perpendicular to the PCB planes
>(rather than parallel) eliminates or at least greatly changes this
>mechanism. As Istvan mentioned, the resonances are very much reduced.
>I believe that there is still an increase in ESR and a reduction of ESL
>beyond series resonance as the current does not want to get very far
>away from the PCB power planes (big inductive loop). Once again, you
>would have to mount the capacitors on very low inductance mounts in
>order to see this.
>
>Regards,
>Larry Smith
>Altera Corporation
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Monday, May 22, 2006 11:27 PM
>To: Hill, John; Mark.Randol@xxxxxxxxxx; si-list
>Subject: [SI-LIST] Re: Capacitors arrays. worth it or not?
>
>John, you've got it. The vertical orientation makes for N very small
>cavities all acting in parallell. Hence, the secondary resonance
>occurs at a much higher frequency.
>
>Regards,
>
>
>Steve.
>At 01:50 PM 5/22/2006, Hill, John wrote:
> >Steve,
> >
> >I'm sorry to be a little thick on this issue, but I may be getting the
> >two orientations confused. If I understand you correctly, the following
> >is true:
> >
> >It is Edie currents that keep the current concentrated in the lower
> >plates of a capacitor when the capacitor is mounted horizontally, which
> >we are defining as having the plates parallel to the board. This
>creates
> >a resonate cavity under the part.
> >
> >When the capacitor is mounted with the plates perpendicular to the
>board
> >the current flows through all the plates.
> >
> >Is this correct?
> >
> >John
> >
> >
> >
> >
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> >---------------------------------------
> >-----Original Message-----
> >
> >From: steve weir [mailto:weirsi@xxxxxxxxxx]
> >Sent: Monday, May 22, 2006 2:41 PM
> >To: Hill, John; Mark.Randol@xxxxxxxxxx; si-list
> >Subject: Re: [SI-LIST] Re: Capacitors arrays. worth it or not?
> >
> >John, when the plates of a cap are parallel to the planes, eddy
> >currents block field penetration to the upper plates through the
> >cavity. The field still goes around the terminal metalization. This
> >makes a resonant cavity.
> >
> >Steve.
> >At 10:50 AM 5/22/2006, Hill, John wrote:
> > >Mark,=20
> > >
> > >We have uploaded an application note from American Technical Ceramics
> > >concerning placing capacitors vertical and horizontal. The URL is:
> > >
> > >http://si-list.org/files/tech_files/ATC%20select_cap_wireless.pdf
> > >
> > >I have also sent an e-mail to the application engineer about the
>issue
> > >of eddy currents limiting the field. The data in the application note
> > >does not look like it supports the idea and I do not understand the
> > >physics.=20
> > >
> > >John
> > >
> > >
> > >=20
> > >
> > >---------------------------------------
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> > >copying, distribution, retention or use of the contents of this
>e-mail
> >=
> > >information is prohibited and may be unlawful. When addressed to
>Takata
> >=
> > >customers or vendors, any information contained in this e-mail is =
> > >subject to the terms and conditions in the governing contract, if =
> > >applicable. If you have received this communication in error, please
>=
> > >immediately notify us by return e-mail, permanently delete any =
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> > >---------------------------------------
> > >-----Original Message-----
> > >
> > >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]
> > >On Behalf Of Mark Randol
> > >Sent: Monday, May 22, 2006 10:33 AM
> > >To: si-list
> > >Subject: [SI-LIST] Re: Capacitors arrays. worth it or not?
> > >
> > > > -----Original Message-----
> > > > From: si-list-bounce@xxxxxxxxxxxxx=3D20
> > > > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Jerry Martinson
> > > >=3D20
> > > > I've always wondered how discrete cap performance is affected=3D20
> > > > if the caps plates are parallel with the underlying plane or=3D20
> > > > if they are perpendicular. I'd think that having them rolled=3D20
> > > > 90 degrees
> > > > (perpendicular) might make them perform better in some=3D20
> > > > regions. I wonder how this would extend to arrays and=3D20
> > > > whether arrays are configured rolled or not. Does anyone=3D20
> > > > know? =3D20
> > >
> > >American Technical Ceramics (ATC) used to recommend 'vertical'
> >placement
> > >of their porcelain caps for just this reason. I've seen it make
> >several
> > >100MHz's of difference in the measured resonance frequency. That was
> >on
> > >a relatively thick 2 layer PCB, so on a board with a thinner
>component
> > >to ground layer spacing this could be more significant <guess>. I
> > >didn't find it on their web site, but here is their link.
> > >
> > >http://www.atceramics.com/
> > >
> > >Now how much of this was due to plate coupling to the substrate, or
> > >reduced effective capacitance and inductance because of current
> >crowding
> > >towards the new 'bottom' of all the plates, beats me. It seems to me
> >in
> > >the horizontal orientation, the upper plates would have slightly more
> > >inductance due to the greater loop area. Which effect dominates,
> > >capacitance or inductance? =3D20
> > >
> > >The problem at the time was fixed, so we didn't investigate further.
> > >
> > >--
> > >Mark Randol, RF Evaluation & Application Engineer
> > >Not speaking for my company, etc
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