[SI-LIST] is clock pair-to-clock pair matching required in DDR?

Guys --
 

We have designed a board with a Freescale powerQUICC processor.  It has 6
separate DDR clock outputs.  We have 5 DDR on-board chips.  My question is -
do we have to match the length of each of the 5 clock-pairs?  I don't quite
understand the need for matching the individual clocks, but this was given
in one of the Freescale app notes.  The app note recommends 20mils matching
within each of the clock pairs.  

We have matched the individual clock pair w.r.t the corresponding DQS within
20mils and DQS to corresponding clock within 250mils.  I feel as long as the
Clock-DQS-Data relationship is maintained, the clock pair-to-pair matching
might not be required.  Would greatly appreciate your help on this.

 

Thanks

Vijay

GDA Technologies Ltd.,

India

www.gdatech.com

 



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