Posts for si-list, 08-2001

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  1. » [SI-LIST] Re: Placement of decoupling capacitors, Greim, Michael
  2. » [SI-LIST] Re: Vp on serpentine, Ingraham, Andrew
  3. » [SI-LIST] Re: EMI and Power plane card edge clearance distance, Dr. Edward P. Sayre
  4. » [SI-LIST] VGA/VIDEO: IMPEDANCE & LENGTH, Chandan
  5. » [SI-LIST] Re: IBIS and device performance, Roy_Leventhal
  6. » [SI-LIST] Re: VGA/VIDEO: IMPEDANCE & LENGTH, stephanie . k . goedecke
  7. » [SI-LIST] Deriving Output Hold Times, Chris Bobek
  8. » [SI-LIST] pci driver strength, IVOR TING
  9. » [SI-LIST] Re: pci driver strength, Ingraham, Andrew
  10. » [SI-LIST] Re: Deriving Output Hold Times, Ingraham, Andrew
  11. » [SI-LIST] Crystal Oscillators, Steinkogler, Gary
  12. » [SI-LIST] OSCILLATOR PHASE NOISE AND LEESON'S EQUATION, Steve Rogers
  13. » [SI-LIST] Re: OSCILLATOR PHASE NOISE AND LEESON'S EQUATION, Ingraham, Andrew
  14. » [SI-LIST] Looking for InfiniBand info/parts/IP/etc., Zabinski, Patrick J.
  15. » [SI-LIST] Re: Scope probe attenuation, Degerstrom, Michael J.
  16. » [SI-LIST] HSpice IBIS Input/Output Buffer syntax, Patrick_Carrier
  17. » [SI-LIST] Re: HSpice IBIS Input/Output Buffer syntax, Adam . Tambone
  18. » [SI-LIST] setup & hold Time for source synchronous, Issa, Elie
  19. » [SI-LIST] Board Design Training Series, Gary Otonari
  20. » [SI-LIST] Re: setup & hold Time for source synchronous, Lai, Ricky (Eng Hou)
  21. » [SI-LIST] SSTL-2 ClassII termination., rajat . chauhan
  22. » [SI-LIST] Reflection on Lattice and Bergeron Diagrams, Abe Riazi
  23. » [SI-LIST] Immunity troubleshooting technique, Douglas C. Smith
  24. » [SI-LIST] Question about Simulation in Spectraquest, whiz kid
  25. » [SI-LIST] Re: Question about Simulation in Spectraquest, Coleman, Dave
  26. » [SI-LIST] Re: Trace layout, Hassan Ali
  27. » [SI-LIST] micro coax cables, Ravikumar Chirugudu
  28. » [SI-LIST] Re: Reflection on Lattice and Bergeron Diagrams, abe riazi
  29. » [SI-LIST] Simulation Question in Spectra Quest., whiz kid
  30. » [SI-LIST] ansoft spicelink training manual, bally
  31. » [SI-LIST] HSTL to LVTTL translation, Bastola, Subas
  32. » [SI-LIST] U and E, Rich Peyton
  33. » [SI-LIST] Re: U and E, Greim, Michael
  34. » [SI-LIST] Re: Controlled impedance test requirement, Dave Hoover
  35. » [SI-LIST] jitter introduced by a mated connector, Kowal, Keith
  36. » [SI-LIST] PCI debugging, Patel, Bhavesh
  37. » [SI-LIST] Re: PCI debugging, Michael Nudelman
  38. » [SI-LIST] Gigabit fiber transceivers, EMI, trace lengths, and... antennas., Kolstad, Joel (EIP)
  39. » [SI-LIST] HSTL for Differential signalling, rajesh . narwal
  40. » [SI-LIST] Can SPICE model CMOS latch-up?, Baoshu XU
  41. » [SI-LIST] Re: jitter introduced by a mated connector, Kai Keskinen
  42. » [SI-LIST] Re: Can SPICE model CMOS latch-up?, Bill . Cohen
  43. » [SI-LIST] EMI, trace lenghts etc..... antennas., Charles Grasso
  44. » [SI-LIST] Timing Methodology (renamed from Question about Simulation in Spectraquest), Scott McMorrow
  45. » [SI-LIST] Resistance, Zhou, Xingling (Xingling)
  46. » [SI-LIST] Abstracts sought for upcoming conference, rfaries
  47. » [SI-LIST] Re: Resistance, Chung, Chee Yee
  48. » [SI-LIST] Antwort: Re: Resistance, Andreas_Lenkisch
  49. » [SI-LIST] Re: Timing Methodology, Chris Cheng
  50. » [SI-LIST] Re: Simulation Question in Spectra Quest., Sivakumar S.
  51. » [SI-LIST] Looking for dist or Rep who offers cut tape for kemet T510 SMT tants, Greim, Michael
  52. » [SI-LIST] Info, Steve Gonzales
  53. » [SI-LIST] Open Position, Hemant Shah
  54. » [SI-LIST] question concerning a PowerPC740, jan . vercammen . jv1
  55. » [SI-LIST] Decoupling capacitor placement, Wei_Chen
  56. » [SI-LIST] HANDLING HIGH-SPEED BURSTs, Lyke James Civ AFRL/VSSE
  57. » [SI-LIST] Re: HANDLING HIGH-SPEED BURSTs, Kowal, Keith
  58. » [SI-LIST] Re: Decoupling capacitor placement, Chung, Chee Yee
  59. » [SI-LIST] Bond Wire Length, Smith, Norm W
  60. » [SI-LIST] Re: Bond Wire Length, Smith, Norm W
  61. » [SI-LIST] IBIS model., fname lname
  62. » [SI-LIST] How does the loading affects the rise time of a PAD?, C.Y. Cheng
  63. » [SI-LIST] Re: IBIS model., Adam . Tambone
  64. » [SI-LIST] Flux residue on coax cable, Rich Peyton
  65. » [SI-LIST] Re: Flux residue on coax cable, Rich Peyton
  66. » [SI-LIST] Re: How does the loading affects the rise time of a PAD?, Michael Nudelman
  67. » [SI-LIST] Double messages, Rich Peyton
  68. » [SI-LIST] alternate subscribe/unsubscribe method for si-list, raymonda
  69. » [SI-LIST] logic analyser measurements at a Controller with 100MHz busses, Roehrner Wolfgang
  70. » [SI-LIST] FW: Announcing a Signal Integrity TC within the EMC Society, Charles Grasso
  71. » [SI-LIST] Re: How does the loading affects the rise time of a PAD ?, Greim, Michael
  72. » [SI-LIST] PCB West 2002 Call for Abstracts, rfaries
  73. » [SI-LIST] Differential closk wiring (with no typos :), BIBICHA
  74. » [SI-LIST] Re: Differential closk wiring (with no typos :), Greim, Michael
  75. » [SI-LIST] CPW r.o.t?, Grossman, Brett
  76. » [SI-LIST] Re: CPW r.o.t?, Raymond W. Waugh
  77. » [SI-LIST] Resistor Network, Patrick Vincent
  78. » [SI-LIST] Re: Resistor Network, Michael Nudelman
  79. » [SI-LIST] Clock quality, Patel, Bhavesh
  80. » [SI-LIST] The doctor's course about SI., Inmyung Song
  81. » [SI-LIST] 100BASE-TX's IBIS model?, Inmyung Song
  82. » [SI-LIST] Re: 100BASE-TX's IBIS model?, Drew
  83. » [SI-LIST] The PLL simulations, chen, jinhua
  84. » [SI-LIST] Re: The PLL simulations, Ingraham, Andrew
  85. » [SI-LIST] Differential delay line sim models, Bastola, Subas
  86. » [SI-LIST] The Doctor course of SI?, Inmyung Song
  87. » [SI-LIST] SPICE vs IBIS, Viral
  88. » [SI-LIST] 2001 RMCEMC Symposium Advance Notice, Charles Grasso
  89. » [SI-LIST] FW: Copper interface cable proposal, Tegan Campbell
  90. » [SI-LIST] Re: FW: Copper interface cable proposal, Rich Peyton
  91. » [SI-LIST] unused clocks, v r
  92. » [SI-LIST] PECL to SSTL2 clock driver, ruston, matt
  93. » [SI-LIST] IDC capacitor, Haller, Robert
  94. » [SI-LIST] Re: PCI at 66 Mhz, Michael Nudelman
  95. » [SI-LIST] Re: unused clocks, Ingraham, Andrew
  96. » [SI-LIST] Re: [Fwd: Re: FW: Copper interface cable proposal], Dima Smolyansky
  97. » [SI-LIST] non-negative off diagonal capacitive matrix elements ??, Ray Anderson
  98. » [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ??, Zhou, Xingling (Xingling)
  99. » [SI-LIST] Spice simulators, Alex Horvath
  100. » [SI-LIST] Relative merits of Spice vs. IBIS, Alex Horvath
  101. » [SI-LIST] Re: Relative merits of Spice vs. IBIS, Greim, Michael
  102. » [SI-LIST] Self Inductance and TDR measurements, Anil Pannikkat
  103. » [SI-LIST] Re: Self Inductance and TDR measurements, Zabinski, Patrick J.