[SI-LIST] Re: Decoupling capacitor placement
- From: Mellberg Hans <htmguy@xxxxxxxxx>
- To: Wei_Chen@xxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Fri, 17 Aug 2001 10:05:30 -0700 (PDT)
In my opinion the best decoupling placement topology
is the one that places the cap as close to the Vxx pin
as possible and minimizing total path inductance. I
prefer to go to the plane as soon as possible and use
the plane instead of a trace. That means vias at the
decoupling cap and vias at the IC pad. Two vias are
better than one as the inductances are reduced. The
total loop inductance must be minimized as well as the
round trip flight time. That means employing all
possible tricks to minimize inductance and distance to
the cap from the IC.
--- Wei_Chen@xxxxxxxx wrote:
>
> There are two ways to place a decoupling capacitor
> for a Vcc pin:
>
> 1. Place the cap on the top-side of the board and
> close together with the
> Vcc pin. Connect Vcc pin to the cap and use two vias
> from the cap to the
> power plane and ground plane. This is pin-cap-via
> topology.
>
> 2. Place the cap on the bottom side of the board
> (under the IC) and close to
> the Vcc pin. Connect Vcc to power plane through a
> via and connect the cap to
> power and ground plane through 2 vias. This is
> pin-via/cap-via topology.
> Basically you used the power plane to connect your
> Vcc pin and decoupling
> capacitor.
>
> This is a multi-power/ground plane board.
>
> Which topology would you recommend?
>
> Thanks,
>
> Wei
>
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