[SI-LIST] Re: Decoupling capacitor placement

Chris,

Your question is similar to this previous post:
http://www.freelists.org/archives/si-list/08-2001/msg00006.html

Also FYI:

1. Istvan Novak shows data for stacked capacitors (up to five in Figure
45,46) in "Overview of Frequency Domain Power Distribution Measurements"
presented at the DesignCon 2003, High-Performance System Design Conference
in San Jose. Here is a link to the paper posted on his website:
http://home.att.net/~inovak/papers/DC03_HP-TF2_SUN.PDF

2. X2Y stacks two matched capacitors inside one capacitor body to reduce
inductance through cancellation. Here's a link to test data on an 1812 size
cap vs. two standard caps. No data on the 0603 yet.
http://www.x2y.com/cube/x2y.nsf/(files)/X2YMLCC.pdf/$FILE/X2YMLCC.pdf


Thanks,
Dave
X2Y





-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
Christopher.Crowley@xxxxxxxxxxxxxxxxx
Sent: Thursday, May 29, 2003 10:25 AM
To: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] Decoupling capacitor placement


Hello,
I am looking to add more decoupling to a high pin count BGA and due to
routing
constraints I am unable to get as close as I would like to the device.
Does anyone
have any experience with making one land pad and then soldering a couple
caps
on top of each other to the one land area?  Say something like a 0603
.01uf on top of
another 0603 .001uf.  I see this as an easy way to get close to the device
as well as reduce
lead and via inductance.  Have I missed something electrically fundamental
or are
there production level assembly issues with this method?

Thanks,
Chris

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