Posts for si-list, 08-2001

Browse: Last Month: 07-2001 Main Archive Page Next Month: 09-2001

» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: Self Inductance and TDR measurements -
» [SI-LIST] Re: Spice simulators -
» [SI-LIST] Self Inductance and TDR measurements -
» [SI-LIST] Spice simulators -
» [SI-LIST] Re: Relative merits of Spice vs. IBIS -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: Relative merits of Spice vs. IBIS -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Relative merits of Spice vs. IBIS -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Spice simulators -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] non-negative off diagonal capacitive matrix elements ?? -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: [Fwd: Re: FW: Copper interface cable proposal] -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] Re: unused clocks -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] Re: PCI at 66 Mhz -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] PCI at 66 Mhz -
» [SI-LIST] Measuring 1.25Gbps differential signals - Triggering Problem -
» [SI-LIST] IDC capacitor -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] Re: SPICE vs IBIS -
» [SI-LIST] Re: The PLL simulations -
» [SI-LIST] Re: PECL to SSTL2 clock driver -
» [SI-LIST] SPICE vs IBIS -
» [SI-LIST] Re: PECL to SSTL2 clock driver -
» [SI-LIST] PECL to SSTL2 clock driver -
» [SI-LIST] unused clocks -
» [SI-LIST] Re: FW: Copper interface cable proposal -
» [SI-LIST] FW: Copper interface cable proposal -
» [SI-LIST] Re: SPICE vs IBIS -
» [SI-LIST] 2001 RMCEMC Symposium Advance Notice -
» [SI-LIST] Re: The PLL simulations -
» [SI-LIST] Re: The PLL simulations -
» [SI-LIST] Re: The PLL simulations -
» [SI-LIST] SPICE vs IBIS -
» [SI-LIST] The Doctor course of SI? -
» [SI-LIST] 100BASE-TX's IBIS Model? -
» [SI-LIST] Differential delay line sim models -
» [SI-LIST] Re: The PLL simulations -
» [SI-LIST] Re: The PLL simulations -
» [SI-LIST] Re: 100BASE-TX's IBIS model? -
» [SI-LIST] The PLL simulations -
» [SI-LIST] Re: Flux residue on coax cable -
» [SI-LIST] Re: 100BASE-TX's IBIS model? -
» [SI-LIST] Re: 100BASE-TX's IBIS model? -
» [SI-LIST] 100BASE-TX's IBIS model? -
» [SI-LIST] The doctor's course about SI. -
» [SI-LIST] Clock quality -
» [SI-LIST] Re: Resistor Network -
» [SI-LIST] Re: Resistor Network -
» [SI-LIST] Re: Resistor Network -
» [SI-LIST] Resistor Network -
» [SI-LIST] Re: CPW r.o.t? -
» [SI-LIST] Re: CPW r.o.t? -
» [SI-LIST] Re: CPW r.o.t? -
» [SI-LIST] Re: CPW r.o.t? -
» [SI-LIST] Re: CPW r.o.t? -
» [SI-LIST] Re: CPW r.o.t? -
» [SI-LIST] CPW r.o.t? -
» [SI-LIST] Re: IBIS model. -
» [SI-LIST] Re: Differential closk wiring (with no typos :) -
» [SI-LIST] Differential closk wiring (with no typos :) -
» [SI-LIST] Differential closk wiring -
» [SI-LIST] Re: IBIS model. -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD ? -
» [SI-LIST] Re: IBIS model. -
» [SI-LIST] Re: Books on SI Model Development and EMI -
» [SI-LIST] Books on SI Model Development and EMI -
» [SI-LIST] PCB West 2002 Call for Abstracts -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD ? -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD? -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD ? -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD? -
» [SI-LIST] FW: Announcing a Signal Integrity TC within the EMC Society -
» [SI-LIST] logic analyser measurements at a Controller with 100MHz busses -
» [SI-LIST] alternate subscribe/unsubscribe method for si-list -
» [SI-LIST] Re: Double messages -
» [SI-LIST] Re: Flux residue on coax cable -
» [SI-LIST] Double messages -
» [SI-LIST] Re: Flux residue on coax cable -
» [SI-LIST] Re: Flux residue on coax cable -
» [SI-LIST] Re: Flux residue on coax cable -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD? -
» [SI-LIST] Re: Flux residue on coax cable -
» [SI-LIST] How does the loading affects the rise time of a PAD? -
» [SI-LIST] Re: How does the loading affects the rise time of a PAD? -
» [SI-LIST] Re: IBIS model. -
» [SI-LIST] Flux residue on coax cable -
» [SI-LIST] Re: IBIS model. -
» [SI-LIST] How does the loading affects the rise time of a PAD? -
» [SI-LIST] IBIS model. -
» [SI-LIST] Re: Bond Wire Length -
» [SI-LIST] Re: Bond Wire Length -
» [SI-LIST] Re: Bond Wire Length -
» [SI-LIST] Re: Decoupling capacitor placement -
» [SI-LIST] Bond Wire Length -
» [SI-LIST] Re: HANDLING HIGH-SPEED BURSTs -
» [SI-LIST] Re: Decoupling capacitor placement -
» [SI-LIST] Re: Decoupling capacitor placement -
» [SI-LIST] Re: HANDLING HIGH-SPEED BURSTs -
» [SI-LIST] HANDLING HIGH-SPEED BURSTs -
» [SI-LIST] Decoupling capacitor placement -
» [SI-LIST] question concerning a PowerPC740 -
» [SI-LIST] Open Position -
» [SI-LIST] Info -
» [SI-LIST] Looking for dist or Rep who offers cut tape for kemet T510 SMT tants -
» [SI-LIST] Re: Timing Methodology -
» [SI-LIST] Re: Simulation Question in Spectra Quest. -
» [SI-LIST] Re: Simulation Question in Spectra Quest. -
» [SI-LIST] Re: Timing Methodology -
» [SI-LIST] Re: Timing Methodology -
» [SI-LIST] Re: Timing Methodology -
» [SI-LIST] Re: Timing Methodology -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Timing Methodology (renamed from Question about Simulation in Spectraquest) -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: Timing Methodology (renamed from Question about Simulation in Spectraquest) -
» [SI-LIST] Re: Resistance -
» [SI-LIST] Re: Timing Methodology (renamed from Question about Simulation in Spectraquest) -
» [SI-LIST] Re: Units Conversion Question -
» [SI-LIST] Re: Units Conversion Question -
» [SI-LIST] Re: Units Conversion Question -
» [SI-LIST] Re: Resistance -
» [SI-LIST] Re: Resistance -
» [SI-LIST] Re: jitter introduced by a mated connector -
» [SI-LIST] Soliciting feedback - latest tool versions -
» [SI-LIST] Re: Resistance -
» [SI-LIST] Re: jitter introduced by a mated connector -
» [SI-LIST] Units Conversion Question -
» [SI-LIST] Re: jitter introduced by a mated connector -
» [SI-LIST] Re: jitter introduced by a mated connector -
» [SI-LIST] Antwort: Re: Resistance -
» [SI-LIST] Re: Resistance -
» [SI-LIST] Abstracts sought for upcoming conference -
» [SI-LIST] Resistance -
» [SI-LIST] Timing Methodology (renamed from Question about Simulation in Spectraquest) -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: HSTL for Differential signalling -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: HSTL for Differential signalling -
» [SI-LIST] EMI, trace lenghts etc..... antennas. -
» [SI-LIST] Re: Can SPICE model CMOS latch-up? -
» [SI-LIST] Re: jitter introduced by a mated connector -
» [SI-LIST] Can SPICE model CMOS latch-up? -
» [SI-LIST] HSTL for Differential signalling -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Gigabit fiber transceivers, EMI, trace lengths, and... antennas. -
» [SI-LIST] Gigabit fiber transceivers, EMI, trace lengths, and... antennas. -
» [SI-LIST] Re: PCI debugging -
» [SI-LIST] PCI debugging -
» [SI-LIST] jitter introduced by a mated connector -
» [SI-LIST] Re: Controlled impedance test requirement -
» [SI-LIST] Re: Simulation Question in Spectra Quest. -
» [SI-LIST] High Frequency/High Speed ... -
» [SI-LIST] Trace layout -
» [SI-LIST] Re: U and E -
» [SI-LIST] Re: U and E -
» [SI-LIST] Re: U and E -
» [SI-LIST] Re: ansoft spicelink training manual -
» [SI-LIST] U and E -
» [SI-LIST] HSTL to LVTTL translation -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: ansoft spicelink training manual -
» [SI-LIST] ansoft spicelink training manual -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: setup & hold Time for source synchronous -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: setup & hold Time for source synchronous -
» [SI-LIST] Simulation Question in Spectra Quest. -
» [SI-LIST] Re: Reflection on Lattice and Bergeron Diagrams -
» [SI-LIST] micro coax cables -
» [SI-LIST] Re: setup & hold Time for source synchronous -
» [SI-LIST] Re: Trace layout -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: Question about Simulation in Spectraquest -
» [SI-LIST] Question about Simulation in Spectraquest -
» [SI-LIST] Immunity troubleshooting technique -
» [SI-LIST] Reflection on Lattice and Bergeron Diagrams -
» [SI-LIST] Re: SSTL-2 ClassII termination. -
» [SI-LIST] SSTL-2 ClassII termination. -
» [SI-LIST] Trace layout -
» [SI-LIST] Re: setup & hold Time for source synchronous -
» [SI-LIST] Re: HSpice IBIS Input/Output Buffer syntax -
» [SI-LIST] Re: HSpice IBIS Input/Output Buffer syntax -
» [SI-LIST] Re: setup & hold Time for source synchronous -
» [SI-LIST] Re: OSCILLATOR PHASE NOISE AND LEESON'S EQUATION -
» [SI-LIST] Board Design Training Series -
» [SI-LIST] setup & hold Time for source synchronous -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: HSpice IBIS Input/Output Buffer syntax -
» [SI-LIST] Eagle Cad tools and Allegro or other design tools -
» [SI-LIST] Re: Scope probe attenuation -
» [SI-LIST] Re: HSpice IBIS Input/Output Buffer syntax -
» [SI-LIST] HSpice IBIS Input/Output Buffer syntax -
» [SI-LIST] Re: Scope probe attenuation -
» [SI-LIST] Re: Scope probe attenuation -
» [SI-LIST] Re: Scope probe attenuation -
» [SI-LIST] Looking for InfiniBand info/parts/IP/etc. -
» [SI-LIST] Re: OSCILLATOR PHASE NOISE AND LEESON'S EQUATION -
» [SI-LIST] Re: OSCILLATOR PHASE NOISE AND LEESON'S EQUATION -
» [SI-LIST] OSCILLATOR PHASE NOISE AND LEESON'S EQUATION -
» [SI-LIST] Crystal Oscillators -
» [SI-LIST] Scope probe attenuation -
» [SI-LIST] Re: pci driver strength -
» [SI-LIST] Re: pci driver strength -
» [SI-LIST] Re: Deriving Output Hold Times -
» [SI-LIST] Re: pci driver strength -
» [SI-LIST] Re: VGA/VIDEO: IMPEDANCE & LENGTH -
» [SI-LIST] pci driver strength -
» [SI-LIST] Deriving Output Hold Times -
» [SI-LIST] Re: VGA/VIDEO: IMPEDANCE & LENGTH -
» [SI-LIST] Re: VGA/VIDEO: IMPEDANCE & LENGTH -
» [SI-LIST] Re: IBIS and device performance -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Re: Vp on serpentine -
» [SI-LIST] Re: Vp on serpentine -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] VGA/VIDEO: IMPEDANCE & LENGTH -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: Vp on serpentine -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Re: Placement of decoupling capacitors -