[SI-LIST] Re: Question about Simulation in Spectraquest

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-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxxxxx]
Sent: Friday, August 10, 2001 9:59 AM
To: Cusanelli, Tony; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Question about Simulation in Spectraquest


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"Cusanelli, Tony" wrote:

>   Are you saying that you need spice simulation?   IBIS will give you the
delay from the output buffer to the thresholds of the
> input buffer.  It stops there, why do you need to go through the buffers?
That delay should be included in the spec for the
> part.

Tony,

For extremely accurate timing, the number specified by the
manufacturer is not very accurate.  It includes package effects.
Unfortunately, even IBIS modeling (somewhat) includes package
effects.  As a result, there is a double counting of some of the
timing and noise margin.  In other cases, some of the noise and
timing margin are discarded.  This all depends upon the methodology
used for simulation and specification.

For accurate timing and noise characterization, it is best to simulate
the entire path from the die to.  Then the question becomes,
where and how do I measure timing?  Well, if the manufacturer specifies
timing to the pin of the device, how do I know how he derrived this number?
Did he use worst case SSO, ISI and crosstalk simulations across corners?
And if he did, how do I remove these effects from my board level simulation
to compensate. (This cannot be done with a standard test load, since a
standard test load knows nothing of crosstalk and SSO package effects.)

It turns out that the timing from die to pin of a device is heavily
influenced
by the noise and switching environment.  Packages are highly coupled
"things", much more so than PC boards, yet we often simulate without
including their coupling at all.  Strange, huh?  This coupling from trace
to trace in the package and from trace to power and ground plane is
critically
important to timing, jitter and noise.  Yet, without a standardized way of
determining how the manufacturer specified his device, we are at a loss
to effectively use the information in the most accurate of ways.  Even
timing to the die pad of the silicon is heavily influenced by the package.
However, timing at internal nodes of the silicon, such as the input to
an output buffer or the output of an input buffer, are not heavily
influenced
by the package, since they are isolated by amplifiers.

Instead, I have concluded that timing for extreme accuracy, should
be performed at the input to the output buffer and the output to the
input buffer, with these buffers included in the simulations.  Why? Because
compared to timing to the pin (or even the die) of a component, timing
at internal nodes of the silicon is extremely stable and can be accurately
characterized without package effects involved.  Then, the remainder of
the timing path can be characterized with an end to end simulation using
the desired package and board characteristics, and applying the necessary
data patterns to fully stimulate the system effects.  In addition, noise can
be added into the powers and grounds to simulate the board power
environment.


regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com





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