[SI-LIST] Can SPICE model CMOS latch-up?
- From: "Baoshu XU" <xbs@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 10 Aug 2001 16:57:06 +0800
Dear SI Gurus,
Does anybody successfully simuated a latch-up effect in CMOS circuit? I am
wondering whether spice can model a latch-up at all. My answer is not except
that the lateral transistors are explicitly included in the spice netlist. what
do you think?
Tell me how if you have done simulation with latch-up.
Best Regards,
Baoshu XU
Signal Integrity Group
Huawei, China
Tel: (86-0755) 6540554
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