[SI-LIST] Re: Can SPICE model CMOS latch-up?

  • From: Bill.Cohen@xxxxxxxxxxxxxxxx
  • To: xbs@xxxxxxxxxx
  • Date: Fri, 10 Aug 2001 09:02:22 -0400


Baoshu XU,

Latch-up on CMOS circuits is a difficult thing to
simulate. Normally in CMOS spice networks
transistors, metal/poly resistors, and transistor
diodes are modelled. For latch-up body contacts,
diffusion/well resistance, and bipolar gain should
be modelled. Since there are normally not models
for these large devices (normal parasitic CMOS
bipolars are small) it would be difficult to extract
these parasitic devices to form networks that can be
simulated for latch-up current triggering.

Through out the years several people in the industry
have successfully simulated to warn of a potential
bad layout situation that could lead to a latch-up
problem. But these would be technology and
design rule specific.

To illustrate the problem I have an example. In
a 0.5u circuit I built an SCR (for a ESD circuit)
that triggered at 3V. In the next generation
technology (0.3u) the same circuit triggered
at 10V. Basically the STI (trench isolation) in
the killed the lateral bipolar gain even though
the circuit layouts were almost identical.

--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components, Circuit Design Group
| Donald Lynch Blvd., 3rd Floor, Marlborough, MA 01752
|
| email: wcohen@xxxxxxxx
| office: (508) 486-1031               fax: (508) 481-8828
--------------------------------------------------------------


                                                                                
                                       
                    "Baoshu XU"                                                 
                                       
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                    si-list-bounce@fre       Subject:     [SI-LIST] Can SPICE 
model CMOS latch-up?                     
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                    08/10/01 04:57 AM                                           
                                       
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                    xbs                                                         
                                       
                                                                                
                                       
                                                                                
                                       




Dear SI Gurus,

Does anybody successfully simuated a latch-up effect in CMOS circuit? I am
wondering whether spice can model a latch-up at all. My answer is not
except that the lateral transistors are explicitly included in the spice
netlist. what do you think?

Tell me how if you have done simulation with latch-up.


Best Regards,


Signal Integrity Group
Huawei, China
Tel: (86-0755) 6540554


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