[SI-LIST] Re: The PLL simulations
- From: Steve Rogers <SRogers@xxxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 28 Aug 2001 08:37:28 +0100
Why not get some test equipment out and measure some things (do people still
do this?)
Is the loop breaking lock or is it just being knocked around a bit? You
could maybe look at the output on a spectrum analyser in zero span at the
PLL frequency. You can then take the Y output of the analyser and plumb that
into an oscilloscope. The scope output is then shows max amplitude when you
are inside the I-F bandwidth of the Spectrum analyser, If you wander outside
the I-F bandwidth the amplitude drops. So..... you should be able to see the
time to lock, and any wandering around in frequency (as long as the wander
is greater that the I-F bandwidth.
Now, How much LF noise do you think you have? Have you measured the suspect
lines?? If you know your VCO gain then you then know the potential frequency
pushing/pulling that you will get (Hz per Volt). If possible you might want
to try to run the synth from a battery to ensure that it is Noise on your
supply rails and not somthing else?
If it is a temperature effect then just maybe you are running out of tuning
range on your synth? One other thing you should be doing is looking at the
VCO control voltage over a temperature sweep (put the thing in the enviro
chamber or a fridge if you havent got a posh chamber). Maybe your synth is
running out of tuning volts at extremes of temp?? This will be obvious (the
VCO control volts will be hard against a rail of very close - you should
allow at least 0.5 volt from rail and ground).
Somthing else that you could have going on is that your loop may not be
stable over temperature. Remember that you need to know what the VCO gain is
at the op temp to do any stability calcs. You should be able to measure the
VCO gain quite easily. In addition if your loop filter components have poor
temperature coeff you could get into trouble ?
You should be able to isolate the problem very quickly with some basic test
kit.
This is the approach I would take, but I just like tinkering. Also, as
somone has already pointed out but not emphasised enough....... simulating
PLL'S is very very very very difficult. This is particularly true in the
region while acquiring lock. I would not believe the results of any
simulation in this area. I think you need to know how you problems are
occurring by doing some tests before you can simulate them (as somone else
has noted, there are lots of coupling mechanisms that can cause you
problems, some I have seen that have made me weep are... power supply
wobbling around due to switching on/off of other parts of system boucing the
supply rails, remember that a lot of good capacitance becomes useless at low
temperature - whats the dielectric? even if this is all working ok if your
not careful with your layout you could end up with large currents flowing a
path which runs under your VCO the small volt drop on the ground plane will
be enough to cause you headaches. ///// Impedance change of the load of the
VCO due to poor buffering of the output, temp could change the load your
working into but this will be a slow change, of more concern is the change
in Z due to switching on/off of the buffer etc////// Feedback into the synth
...... heaps of ways this can occur as im sure you are aware. The effects
are various, can knock you in and out of lock or just modulate the VCO a
bit. One other thing that is often useful to do is modulate the synth first
with a sine wave then with a square wave.Compare the original mod waveform
with the de-mod version from the synth. This tells you lots. You can sweep
the mod frequency with the sine wave and measure the real loop response (you
absolutely must do this and in your case over temp). The next one is the
square wave, you can see the response of the loop to a square waveform
(nice). In particular it will tell you if your loop filter is right... often
the loop can nibble off your low frequency components leaving you with
droopy top square waves. The other way you get the shark fin slow rise/fall
due to high frequency or lack thereof of HF response.
My final words
Good Luck!!!!!!
Steve
Steve Rogers B.Eng (Hons) AMIEE
RF Design Engineer
Micromill Electronics Limited
Tel: +44 (0) 23 9236 6600
Fax: +44 (0) 23 9236 6673
SRogers@xxxxxxxxxxxxx
Micromill Electronics Limited, Leydene House, Waterberry Drive,
Waterlooville, Hants, PO7 7XX, United Kingdom
Registration No. 1456922 (England). Registered office as above.
> -----Original Message-----
> From: chen, jinhua [SMTP:chen_jinhua@xxxxxxx]
> Sent: 27 August 2001 06:14
> To: SI LIST
> Subject: [SI-LIST] The PLL simulations
>
>
> Hi, SIer's
>
> I had a problem with PLL circuit recently. The PLL circuit was
> part of Gigabit SerDes device. When the device was tested in the low
> temperature, the SerDes got a lots of bit-errors. We figured
> out that the low frequency power noise got into the circuit and
> the PLL could not lock the clock. Then it caused the high bit-error
> rates.
>
> I want to simulate this problem with different temperature, different
> supply voltage levels and different noise levels with different=20
> frequencies. Theoretically, the HSPICE should be able to do it.=20
> I never simulated the PLL before. Anybody can shed some light on
> this issue? If the SPICE is not a good tool to do it, any other
> tools available to make such simulations?
>
> Thanks!
>
> Jinhua Chen
> Consulting Design Engineer
> 171 South St.
> Hopkinton, MA 01748
> 508-435-1000, ext. 15285
> Pager: 8779700234
> chen_jinhua@xxxxxxx
>
> EMC=B2 =20
> The Enterprise Storage Company
>
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