[SI-LIST] Re: The PLL simulations
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
- To: 'si-list' <si-list@xxxxxxxxxxxxx>
- Date: Mon, 27 Aug 2001 13:42:41 -0400
If you know that the HSPICE model is sufficiently complete, including
whatever coupling mechanism causes the jitter, then it should do it.
However, simulating a PLL at the transistor level with SPICE can be painful.
You might be looking at effects that occur over thousands or even millions
of cycles (VCO start-up and stabilization time, PLL loop dynamics), and
SPICE is chugging along with much smaller time increments. If SPICE does a
few thousand iterations to complete one VCO cycle, and you want to see a
sequence of a million cycles ... you get the idea.
In your case, you might not need to actually "see" the PLL lock up (which
itself can take thousands of cycles) and track the input. Maybe all you
want to do is observe and measure crosstalk into node "X" as you vary
certain parameters. So maybe it's not so bad....
Regards,
Andy
> ----------
> I want to simulate this problem with different temperature, different
> supply voltage levels and different noise levels with different=20
> frequencies. Theoretically, the HSPICE should be able to do it.=20
> I never simulated the PLL before. Anybody can shed some light on
> this issue? If the SPICE is not a good tool to do it, any other
> tools available to make such simulations?
>
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