[SI-LIST] Re: The PLL simulations

  • From: "H H Goh" <gohhh@xxxxxxxxxxxxxx>
  • To: "'si-list'" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 28 Aug 2001 02:22:31 +0800

Yes, I agree with Andy.  Simulating a PLL at the transistor level with
SPICE/HSPICE can be painful and it may take days to get the result that you
want.

Our company do full Custom tailor-made IP including PLL.   Instead of using
HSPICE, we use HSIM to simulate the PLL.  You will get the simulation result
at a much much short time as compare to HSPICE and with 1%-2% accuracy as
compare to HSPICE.

Hope this help.

For your info, we are HSIM distributor in Singapore.  Not promoting the
product but just trying to help

H H Goh

****************************************************************************
************
H H Goh                                           Email: hhgoh@xxxxxxxxxxxx
Technical Manager                               Website:
http://www.spsda.com.sg
SPS-DA Pte Ltd           Tel: (65) - 8906938 / 8906939 (DID)
3 International Business Park                Fax: (65) - 8960928
#03-18/19 Nordic European Centre         HP: (65) - 97537484
Singapore 609927
****************************************************************************
************


----- Original Message -----
From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
To: "'si-list'" <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, August 28, 2001 1:42 AM
Subject: [SI-LIST] Re: The PLL simulations


>
> If you know that the HSPICE model is sufficiently complete, including
> whatever coupling mechanism causes the jitter, then it should do it.
>
> However, simulating a PLL at the transistor level with SPICE can be
painful.
> You might be looking at effects that occur over thousands or even millions
> of cycles (VCO start-up and stabilization time, PLL loop dynamics), and
> SPICE is chugging along with much smaller time increments.  If SPICE does
a
> few thousand iterations to complete one VCO cycle, and you want to see a
> sequence of a million cycles ... you get the idea.
>
> In your case, you might not need to actually "see" the PLL lock up (which
> itself can take thousands of cycles) and track the input.  Maybe all you
> want to do is observe and measure crosstalk into node "X" as you vary
> certain parameters.  So maybe it's not so bad....
>
> Regards,
> Andy
>
>
> > ----------
> > I want to simulate this problem with different temperature, different
> > supply voltage levels and different noise levels with different=20
> > frequencies. Theoretically, the HSPICE should be able to do it.=20
> > I never simulated the PLL before. Anybody can shed some light on
> > this issue? If the SPICE is not a good tool to do it, any other
> > tools available to make such simulations?
> >
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>


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