Posts for si-list, 07-2001

Browse: Last Month: 06-2001 Main Archive Page Next Month: 08-2001

» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Vp on serpentine -
» [SI-LIST] Re: Placement of decoupling capacitors -
» [SI-LIST] Re: differential trace mismatch -
» [SI-LIST] Design with DDR (SSTL-2) memory -
» [SI-LIST] Re: differential trace mismatch -
» [SI-LIST] Re: Rise time calculation -
» [SI-LIST] Re: PCI Bus Ringing, Overshoot -
» [SI-LIST] Re: Rise time calculation -
» [SI-LIST] Fiber Channel simulation -
» [SI-LIST] Placement of decoupling capacitors -
» [SI-LIST] PCI Bus Ringing, Overshoot -
» [SI-LIST] Re: Alloy-42 ur and sigma ... -
» [SI-LIST] Alloy-42 ur and sigma ... -
» [SI-LIST] differential trace mismatch -
» [SI-LIST] Re: Tool Recommendations? -
» [SI-LIST] Re: ac drive strength -
» [SI-LIST] Rise time calculation -
» [SI-LIST] Creating IBIS Electrical Board Descriptions -
» [SI-LIST] IBIS and device performance -
» [SI-LIST] Re: AMD Forms Hyper-Transport I/O Consortium -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] HSPICE to print HEX question -
» [SI-LIST] Re: ac drive strength -
» [SI-LIST] Re: Tool Recommendations? -
» [SI-LIST] Re: ac drive strength -
» [SI-LIST] Re: ac drive strength -
» [SI-LIST] Re: IBIS Model for Multi-Chip Package -
» [SI-LIST] Re: IBIS Model for Multi-Chip Package -
» [SI-LIST] Re: LVDS Glitch Problem -
» [SI-LIST] Re: LVDS Glitch Problem -
» [SI-LIST] Re: Tool Recommendations? -
» [SI-LIST] LVDS Glitch Problem -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: Results of the "Reply To:" survey - Option B wins -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: EMI and Power plane card edge clearance distance -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] EMI and Power plane card edge clearance distance -
» [SI-LIST] Results of the "Reply To:" survey - Option B wins -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: IBIS Model for Multi-Chip Package -
» [SI-LIST] IBIS Model for Multi-Chip Package -
» [SI-LIST] Re: Tool Recommendations? -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] AMD Forms Hyper-Transport I/O Consortium -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] Re: diff pair questions -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] Re: si-list administrivia -
» [SI-LIST] si-list administrivia -
» [SI-LIST] Re: Tool Recommendations? -
» [SI-LIST] Tool Recommendations? -
» [SI-LIST] diff pair questions -
» [SI-LIST] Re: SpecctraQuest -
» [SI-LIST] test message - Ignore and Delete -
» [SI-LIST] Re: Transmission line simulation at 1.25GHZ -
» [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION -
» [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION -
» [SI-LIST] Re: SpecctraQuest -
» [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION -
» [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION -
» [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION -
» [SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION -
» [SI-LIST] AGP model -
» [SI-LIST] Transmission line simulation at 1.25GHZ -
» [SI-LIST] Re: ac drive strength -
» [SI-LIST] Re: Question about package models -
» [SI-LIST] Re: need some help -
» [SI-LIST] Re: need some help -
» [SI-LIST] Re: ac drive strength -
» [SI-LIST] need some help -
» [SI-LIST] ac drive strength -
» [SI-LIST] Re: Question about package models -
» [SI-LIST] LICA in flip chip BGAs -
» [SI-LIST] PCB material with er=2.5? -
» [SI-LIST] Buried Resister in High speed digital design? -
» [SI-LIST] Last Day in Force -
» [SI-LIST] System Designers w/ SI skills needed in Santa Clara, CA -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: tools for assembly cost and metrics of printed circuit boards -
» [SI-LIST] Re: decoupling -
» [SI-LIST] set si-list vacation -
» [SI-LIST] tools for assembly cost and metrics of printed circuit boards -
» [SI-LIST] Re: Controlled impedance PCB question -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Mictor probes and 'high' speed/sensitive signals -
» [SI-LIST] Flash memory -
» [SI-LIST] Re: Question about package models -
» [SI-LIST] Re: Question about package models -
» [SI-LIST] Re: Controlled impedance PCB question -
» [SI-LIST] Re: Question about package models -
» [SI-LIST] Re: Controlled impedance PCB question -
» [SI-LIST] Question about package models -
» [SI-LIST] Re: Controlled impedance PCB question -
» [SI-LIST] Controlled impedance PCB question -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] High Speed Inter-board connections -
» [SI-LIST] Re: Clock skew measurement using XTK simulation tool -
» [SI-LIST] Oscilloscope for POST SI Analysis -
» [SI-LIST] IBIS model -
» [SI-LIST] Clock skew measurement using XTK simulation tool -
» [SI-LIST] Buried resister in High Speed Digital Design? -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: Injecting noise into a plane -
» [SI-LIST] Re: Injecting noise into a plane -
» [SI-LIST] Re: Injecting noise into a plane -
» [SI-LIST] SMT headers vs. SMA -
» [SI-LIST] Re: Injecting noise into a plane -
» [SI-LIST] Injecting noise into a plane -
» [SI-LIST] Re: In EBD model? -
» [SI-LIST] Re: Production testing of loaded PCB's power supply impedance -
» [SI-LIST] Production testing of loaded PCB's power supply impedance -
» [SI-LIST] Re: In EBD model? -
» [SI-LIST] Re: In EBD model? -
» [SI-LIST] In EBD model? -
» [SI-LIST] Re: Looking for Oztek and special SMA's -
» [SI-LIST] Re: IC Receiver Design for Low Jitter -
» [SI-LIST] Re: IC Receiver Design for Low Jitter -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: Temperature vs. performance in different type of processes. -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: Temperature vs. performance in different type of processes. -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: extraction of RLGC matrices from Sigexplorer -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Signal Integrity Position - ASIC : Cisco Systems, Inc. San Jose, CA -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: Looking for Oztek and special SMA's -
» [SI-LIST] Re: IC Receiver Design for Low Jitter -
» [SI-LIST] Re: Looking for Oztek and special SMA's -
» [SI-LIST] Re: Looking for Oztek and special SMA's -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Looking for Oztek and special SMA's -
» [SI-LIST] Re: IC Receiver Design for Low Jitter -
» [SI-LIST] Re: IC Receiver Design for Low Jitter -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] IC Receiver Design for Low Jitter -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] Re: On-chip Terminations -
» [SI-LIST] On-chip Terminations -
» [SI-LIST] Re: Primary Signal Integrity Hardware Tools -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: Primary Signal Integrity Hardware Tools -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: extraction of RLGC matrices from Sigexplorer -
» [SI-LIST] Re: extraction of RLGC matrices from Sigexplorer -
» [SI-LIST] Re: extraction of RLGC matrices from Sigexplorer -
» [SI-LIST] Re: Primary Signal Integrity Hardware Tools -
» [SI-LIST] extraction of RLGC matrices from Sigexplorer -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: Primary Signal Integrity Hardware Tools -
» [SI-LIST] Primary Signal Integrity Hardware Tools -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: Board to Board connetcions using Coax cables -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: post layout SI analysis -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: Board to Board connetcions using Coax cables -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Board to Board connetcions using Coax cables -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] post layout SI analysis -
» [SI-LIST] Re: power plane spacing -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: Temperature vs. performance in different type of processes. -
» [SI-LIST] Re: decoupling -
» [SI-LIST] stats si-list -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Temperature vs. performance in different type of processes. -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Re: FR4 -
» [SI-LIST] Re: Which computing platform for (Ansoft/Pacific Numerix) TPA -
» [SI-LIST] si-list hardware failure on 7/7 thru 7/9 -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: decoupling -
» [SI-LIST] Re: High performance materials -
» [SI-LIST] FR4 -
» [SI-LIST] Re: Validation of XTK results for clock skews -
» [SI-LIST] Re: Decoupling -
» [SI-LIST] Re: Decoupling -
» [SI-LIST] Which computing platform for (Ansoft/Pacific Numerix) TPA -
» [SI-LIST] Re: ADDITIONAL PCI CLOCKS -
» [SI-LIST] High performance materials -
» [SI-LIST] ADDITIONAL PCI CLOCKS -
» [SI-LIST] Re: Validation of XTK results for clock skews -