[SI-LIST] SSTL-2 ClassII termination.
- From: rajat.chauhan@xxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 4 Aug 2001 17:06:04 +0530
Hello all,
JEDEC8-9A specifies AC test enviorment for SSTL_2 ClassII driver,
shown below. This means that the driver design will be optimized for this
enviorment (though may used in other enviorments).
___ 1.25V ___ 1.25V
| |
\ \
/ 50 ohms. / 50ohms
\ \
|\ 25 ohms / ____________ /
| \----^^^^^^--|--I____________I--I
| / Rs TL |
|/ __|__
Driver _____ Cload
|
__|__
//////
But I have seen in some of it's application (DDR SDRAM signaling) it is
used with the scheme shown below.
___ 1.25V
|
\
/ 25ohms
\
|\ 25 ohms ____________ /
| \----^^^^^^-----I____________I--I
| / Rs TL |
|/ __|__
Driver _____ Cload
|
__|__
//////
My question is:
1. What is the difference between the two and when one is preferred over
the other?
2. Some pappers also says that series resistor Rs isolates the stubs from
main memory bus. HOW?
With Best Regards,
Rajat
STMicroelectronics
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