[SI-LIST] Re: PECL to SSTL2 clock driver
- From: "S. Weir" <weirsp@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 28 Aug 2001 15:47:56 -0700
For a clock, I prefer capacitive coupling over Thevenin as it attenuates
supply noise below the cutoff, which can be helpful for jitter reduction.
Regards,
Steve.
At 02:57 PM 8/28/01 -0700, D. C. Sessions wrote:
>On Tuesday 28 August 2001 14:40, ruston, matt wrote:
>
> > Does anyone know of an SSTL2 clock driver that accepts PECL inputs
> (without
> > having to shift the differential clk input levels)? I'm looking at
> something
> > like the TI CDCV850. Does anyone have any experience with this chip? Thanks
> > for the help...
>
>I don't see the problem with shifting. PECL (at least the 3.3v version)
>has an output common mode voltage of 1.98 v. SSTL-2 has an input
>common mode of 1.25 v. Since you have to terminate anyway, why
>not just terminate the SSTL-2 inputs to Vtt and connect the PECL
>outputs through blocking caps?
>
>Alternately, you can just divide down with Thevenin networks.
>Not perfect, but for two lines no big deal and 500 mV is plenty
>for SSTL-2 inputs.
>
>--
>| The race is not always to the swift, nor the battle to the strong. |
>| Because the slow, feeble old codgers like me cheat. |
>+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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