Posts for si-list, 03-2009

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  1. » [SI-LIST] final note on XTK, eric bogatin
  2. » [SI-LIST] Advantages & Disadvantages of Flooding Vias??, ManatoshGBaidya
  3. » [SI-LIST] Central Pennsylvania's Third Symposium on Signal Integrity, Clewell, Craig
  4. » [SI-LIST] Re: 180 degree turns in high speed lines, Eugenio Simões
  5. » [SI-LIST] March 2009 Technical Tidbit - Current Probes, More Useful Than You Think - Part 3, Doug Smith
  6. » [SI-LIST] question about voltage dividers, Roy M
  7. » [SI-LIST] Xilinx SpartanT-3/3E/3L FPGA Power Solutions-- From Monolithic Solutions, Vivekkumar M-TLS,Chennai
  8. » [SI-LIST] footprint for 100-pin Hirose FX2 socket connector, chao wang
  9. » [SI-LIST] Re: general belief about Xtalk, Howard Johnson
  10. » [SI-LIST] Senior Signal Integrity opening with Juniper Networks (Sunnyvale, CA), Luong
  11. » [SI-LIST] Packaging Opportunity at AMCC/Either in Sunnyvale or San Diego, Dev Malladi
  12. » [SI-LIST] How to simulate worse case eye, Joel Brown
  13. » [SI-LIST] Center Resonance Frequency in calculating the Q of System, Lakshmi Narayanan Sowrirajan, TLS-Chennai
  14. » [SI-LIST] Impedance match of a 100Mhz line, Barthi das
  15. » [SI-LIST] FW: Center Resonance Frequency in calculating the Q of System, Lakshmi Narayanan Sowrirajan, TLS-Chennai
  16. » [SI-LIST] High-Speed (coax) PCB Connector Transitions -- selection, PCB footprint, and performance, Michael Rodrigues
  17. » [SI-LIST] What is 'Integrated RMS jitter' and how is it measured, Henrik G Madsen
  18. » [SI-LIST] layer stackup assignment, Jie Wang
  19. » [SI-LIST] Re: layer stackup assignment, olaney
  20. » [SI-LIST] Potentially Dumb Question About Routing Layers, Nash, Timothy J
  21. » [SI-LIST] Transceiver Design Workshop with Dr. Eric Bogatin - April 2, 2009, Salman Jiva
  22. » [SI-LIST] Patch Antenna Design for UHF RFID reader, Vinod Kumar
  23. » [SI-LIST] rush of current at power on, sunil bharadwaz
  24. » [SI-LIST] V-level of LVDS jitter measurement, Peterson, James F (EHCOE)
  25. » [SI-LIST] hi, navaram kumar
  26. » [SI-LIST] Transmission Line calculator Problem!, Mohamad Haghtalab
  27. » [SI-LIST] Re: Transmission Line calculator Problem!, Lee Ritchey
  28. » [SI-LIST] European IBIS Summit @ DATe 2009 - Third Call for Participation, Ralf Brüning
  29. » [SI-LIST] Re: How to simulate worse case eye, Todd Westerhoff
  30. » [SI-LIST] Tutorial needed, Mohamad Haghtalab
  31. » [SI-LIST] homework, salammon@xxxxxxxx
  32. » [SI-LIST] Re: Tutorial needed, fpz
  33. » [SI-LIST] Re: homework, salammon@xxxxxxxx
  34. » [SI-LIST] S-parameter file viewing tool, Peter . Pupalaikis
  35. » [SI-LIST] [RESEND] European IBIS Summit @ DATe 2009 - Third Call for Participation, Ralf Brüning
  36. » [SI-LIST] command line impedance calculator, Sanjeev Gupta
  37. » [SI-LIST] USB 3.0 questions, J. Eric Gamble
  38. » [SI-LIST] Signal Integrity for PCB Designers, V S
  39. » [SI-LIST] FW: PI Analysis doubts (please help) - Plane pair problem, Lakshmi Narayanan Sowrirajan, TLS-Chennai
  40. » [SI-LIST] PI Analysis doubts (please help) - Plane pair problem, Lakshmi Narayanan Sowrirajan, TLS-Chennai
  41. » [SI-LIST] PS/2 Mouse Interface protocol, chao wang
  42. » [SI-LIST] timing analysis, Harwood, Morton (GE Infra, Aviation, US)
  43. » [SI-LIST] Loop inductance of regulator, Lakshmi Narayanan Sowrirajan, TLS-Chennai
  44. » [SI-LIST] About Hspice warning, fangod
  45. » [SI-LIST] Re: PS/2 Mouse Interface protocol, liuluping 41830
  46. » [SI-LIST] Re: timing analysis, Robert Szumowicz
  47. » [SI-LIST] RF Shiled, sunil bharadwaz
  48. » [SI-LIST] A question about Rocketio hspice model, fangod
  49. » [SI-LIST] Who wants 5 minutes of fame?, eric bogatin
  50. » [SI-LIST] 姚潔茹感覺他的陰莖好粗把自己久曠的陰道撐得滿滿的, f83118
  51. » [SI-LIST] Question about the usage of package model(.pkg) in IBIS and the [Package] parameter, Seshadri Venkataramanan
  52. » [SI-LIST] Straw poll: Which phrase best describes your usage of IBIS AMI?, colin_warwick