[SI-LIST] V-level of LVDS jitter measurement
- From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 12 Mar 2009 16:41:57 -0400
SI experts,
We are trying to make a careful jitter measurement of an LVDS clock.
It's a SERDES reference clock running at about 50MHz.
We are seeing way more jitter than expected. The trigger point right now
looks like it is at the cross point of the diff signals (vdiff = 0v).
Shouldn't that be changed to around 50mv or 100mv?
Thanks in advance.
Jim Peterson
Honeywell
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
