[SI-LIST] Re: PI Analysis doubts (please help) - Plane pair problem
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: "Lakshmi Narayanan Sowrirajan, TLS-Chennai" <lakshminarayanans@xxxxxx>
- Date: Mon, 23 Mar 2009 09:16:04 -0400
Dear Lakshminarayanan,
As Steve pointed out, there can be significant differences at high
frequencies whether you assume
point source and point load versus distributed source and/or load. The
calculations in Chapter 5
of Power Distribution Design Methodologies refer to a point of load CPU
core power distribution
network. The approach described there stays valid also for applications
where the source or load
are distributed, but in addition to the steps shown there, you also need
to consider the placement
of parts, and/or possibly using additional components to deal with the
lumped resonance coming
from the static capacitance of planes and cumulative inductance of
bypass capacitors, as well as
all the modal resonances of the planes.
The overall PDN solution (number and values of capacitors and their
types) has many considerations
to go into it, so eventually when one considers what solution to use, we
need to look at the full picture.
System density, reliability requirement, component-placement
limitations, height limitations among
others may go into the final decision. So on paper one solution may
look overdesigned if those
other constraints are not considered. Some capacitors are very cheap,
but if we use many of them,
the assembly cost, and even more importantly the real-estate on the
board may quickly swamp out
the cost benefit. Your best approach is to learn the options, look at
your input data and other
constraints and base the design on those inputs. Dont judge a solution
purely based on the number
of parts; on some popular computer boards you will find hundreds (and
thousands!) of bypass
capacitors; it is all about the proper tradeoffs between cost, size and
required performance.
Regards,
Istvan Novak
SUN Microsystems
Lakshmi Narayanan Sowrirajan, TLS-Chennai wrote:
> Dear All,
>
>
>
> There is some problem in the mailbox of min, so the
> attachment is not through and the mail was not clear in my last request.
> Sorry for the same.
>
>
>
> Here are the details...
>
>
>
> Problem 1:
>
>
>
> 1 --------------------------- => GND
>
>
>
> 2 +++++++++++++++ => VCC_1.0V
>
>
>
> 3 --------------------------- => GND
>
>
>
> With the above stack-up for the board I have taken first the 2&3 pair
> alone and simulated with cadence PI tool, where I got a normal result
> with one 470uF suppressing the noise up to 6MHz
>
>
>
> Then I included the pair 1&2 to the simulation and proceeded with the
> multi plane simulation, were the result is some thing I don't
> understand...!!!. The reason is with one 470uF it is able to suppress
> the noise up to 10G and more. Please explain this what is the problem,
> in the stackup or in the multi plane analysis.
>
>
>
>
>
> Problem2:
>
>
>
> For 1.0V, 2.1A dynamic current and 20uS response of the regulator I am
> trying to get the decap values. Can any body suggest some easy method of
> spreading the capacitor across the spectrum....? My board operating
> frequency is 600MHz so hopefully I have to suppress the noise up to
> atleast 1200 to 1800MHz
>
>
>
> I have tried many methods as below
>
>
>
> 1) Method described in Black Magic book, the number of capacitor
> is coming nearly 170
>
> 2) Method described in Power Distribution Network Design
> Methodologies chapter 5 (Barry William) there I am not able to get the
> results reflected in the cadence PI tool
>
>
>
> Is there any other method which can give the spreading of capacitor
> across the required spectrum..?
>
>
>
> Hopping to get a positive reply from the group
>
>
>
>
>
>
>
> General Question: In SILIST can we attach files to the mails....I am not
> able to send any attachments. Please give your suggestions
>
>
>
>
>
> Thanks in advance
>
>
>
> Regards,
>
> Lakshminarayanan.S
>
>
>
>
>
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