[SI-LIST] Timing analysis between PXA270 and CPLD
- From: "Vivekkumar M-TLS,Chennai" <Vivekkumarm@xxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 10 Mar 2009 18:28:06 +0530
Dear All,
We have interfaced PXA270 processor to a Cool Runner-2 CPLD in our
design.Following are my queries:
1)If any of you have used the processor before, could you please let me
know which timing diagram I need to take for reference to compare with
the CPLD timings. Is it the VLIO interface or GPIO timing spec??
2)What are the inputs required from CPLD side. Iam having the Timing
report file generated from the deisgn file in Xilinx.
3)Please can anyone of you suggest us how to check if the timing
requirement of the processor( say setup,hold time) meets with the cpld..
Is there any specific way.
Please give in your comments.
Thanks
Regards
Vivek.
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