[SI-LIST] Re: How to simulate worse case eye
- From: "Dmitriev-Zdorov, Vladimir" <vladimir_dmitriev-zdorov@xxxxxxxxxx>
- To: "QU Perry" <Perry.Qu@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 10 Mar 2009 11:26:59 -0600
Hi Perry,
In fact, you may choose between at least 3 different simulators when
running for step or impulse response in Hyperlynx (including HSPICE;
they are integrated). The result of this test simulation is fed directly
to FastEye engine that is a part of Hyperlynx and performs fast time
domain, worst case and statistical analysis for eye diagram/BER etc.
>I was thinking about feeding a PRBS31 pattern into a 8b/10B encoder and
use >the output of encoder as input excitation in simulation.
Yes, this is a good idea. In "fast" time domain analysis, we support
pseudo random generation of the 8b/10b pattern, but we do not base this
generation on any cyclic source, like LFSR, to avoid periodicity. This
way we may get any combination that does fit into 8b/10b constrains.
However, even though 8b/10b is a subclass of general unconstrained
pattern, it still has sufficient "variability" preventing us from
finding the worst case by simply performing long simulation. For
example, some time ago, we performed an experiment where such non-cyclic
"pseudo random" 8b10b pattern was running on 1 trillion = 1e12 bits
(took about 3 weeks to complete). Still, the resulting eye contour was
unable to approach to a 100 bit long worst 8b10b combination that can be
found from the worst case analysis in a fraction of a second. The eye
height that the worst pattern provided was about 12% smaller than we get
from this long simulation.
My guess is that PRBS7 is often used as a substitute for 8b10b, because
it has approximately same running length. However, it still may have 7
ones in a row, and in a long run, it does not support disparity between
its 4/6 bit words, and globally: with 127 bit period, it simply cannot
contain equal number of ones and zeros.
Vladimir
There is a tutorial video showing how you use HyperLynx FastEye in v7.7
which is the tool that generates the worst case bit sequence.
http://supportnet.mentor.com/reference/tutorials/50024.cfm
There is also a possibility to get the license and try the new beta
version that is more flexible in terms of providing channel
characterization.
-----Original Message-----
From: QU Perry [mailto:Perry.Qu@xxxxxxxxxxxxxxxxxx]
Sent: Tuesday, March 10, 2009 10:32 AM
To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx
Cc: Oh, Dan
Subject: RE: [SI-LIST] Re: How to simulate worse case eye
Hi, Vladimir:
Would you be able to provide some more details on the simulation flow
you mentioned using Hyperlynx? If I understand correctly, you extract
step response or pulse response separately in Hspice and then feed that
waveform into HL for worst case eye simulation ? Do we need the new
version of HL for that (8.0)?
I also share your observation on using long PRBS pattern on AC coupled
serdes channel can be over-pessimistic for 8b/10b encoded system from DC
balance point of view. PRBS7 on the other hand does provide enough
pattern variation and can be too optimistic. I was thinking about
feeding a PRBS31 pattern into a 8b/10B encoder and use the output of
encoder as input excitation in simulation. We asked Synopsys to add
8b/10b encoder in LSFR function and they agreed to do that.
Dan: I'm interested in your paper. Can you please send me a copy?
Thanks!
Perry
=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu@xxxxxxxxxxxxxxxxxx
=======================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Dmitriev-Zdorov, Vladimir
Sent: Saturday, March 07, 2009 10:02 AM
To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: How to simulate worse case eye
Tim/Joel,
Perhaps, I should have given more details in my previous reply.
Yes, the paper of Brian Casper, and even some earlier works give us a
method of building an unconstrained worst case pattern; that is
relatively simple. I would also recommend reading this paper as an
excellent introduction into the topic.
However, this approach does not answer all practical needs, including
the following.
1. Encoded worst case pattern. In many important cases the
unconstrained worst case solution does not have much value. If e.g. the
SERDES channel includes series capacitor(s), we know that the eye will
be closed by sufficiently long series of logical 'ones' or 'zeros'. The
longer is a series of identical bits, the more closed the eye becomes.
In this sense, there is no 'worst' unconstrained solution, unless the
pattern length is limited. Of course, in such channels only encoded
binary inputs are allowed (8b10b or some others), with their imparity
and running length constraints, for which the idea of 'worst case
pattern' makes a perfect sense. There exists a solution for such case in
HL.
2. Some types of non-LTI behavior. For example, in many cases the
responses to rising and falling transitions are not symmetrical, that
means their sum R(t) + F(t) is not identical constant. There are several
sources of this phenomenon: (a) persistent time shift between R/F
transitions (DCD), (b) asymmetry of PU and PD I-V or timing
characteristics in a single ended channel, or (c) partial conversion of
near end common signal into far end differential signal, that may occur
even with identical differential buffers, if linear part of the channel
is not ideally symmetric (creates differential skew).
In the recent Mentor/Tek paper "New methods of measuring the performance
of equalized serial data links and correlation of performance measures
across the design flow..." from DesignCon2009 we considered worst case
solutions, including cases (1), (2) and combination of (1) and (2).
>
>
>
>
Joel,
I'm sure there will be no shortage of recommendations here, but here's
my contribution:
It's pretty easy to determine the worst case pattern for a single route,
assuming the system is linear-time-invariant.
1. Start by generating the pulse response of the system.
2. Then sample the response at UI intervals from the Peak or cursor
sample, or just eyeball the ISI at these intervals.
3. Based on the direction or polarity of the ISI terms, and their
relative distances from the cursor (in UI), you can determine what input
pattern can be used to maximize the combined contributions of the ISI
terms. Positive-going ISI terms eat away from the nominal zero level,
and negative-going ISI terms eat away from the nominal one level.
4. You can then move your cursor away from the peak of the pulse
response and repeat the process to determine patterns targeting points
across the width of the eye if desired.
If you haven't read it, check out Bryan Casper's paper describing the
use of Peak Distortion analysis to generate Worst Case Eyes. It doesn't
explicitly tell you how to generate the worst case pattern, but it may
inspire you.
B.K. Casper, et al, "An accurate and efficient analysis method for
multi-Gb/s chip-to-chip signaling schemes."
If you've got IEEE access:
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber15043&isnumber!8
31
Tim Hollis
DRAM Design
Micron Technology, Inc.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Joel Brown
Sent: Friday, March 06, 2009 3:35 PM
To: SI-LIST@xxxxxxxxxxxxx
Subject: [SI-LIST] How to simulate worse case eye
I was watching a webinar by Mentor on Hyperlynx and how they can quickly
generate a prbs pattern that results in a worse case eye diagram. They
said
without this feature it could take days or even years of simulation to
do
this.
I do most of my simulation in hspice since most of my models are based
in
Hspice.
Is there a way to do what Mentor is claiming in Hspice by generating a
certain pattern?
I have been using the following code for a prbs sequence:
vin inr vcm LFSR(0.1 -0.1 1n 5ps 5ps
+ 'data_rate' 1 [7,4,1] rout=0)
vinn innr vcm LFSR(-0.1 0.1 1n 5ps 5ps
+ 'data_rate' 1 [7,4,1] rout=0)
Thanks - Joel
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