[SI-LIST] Re: layer stackup assignment
- From: olaney@xxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 11 Mar 2009 13:08:45 -0700
Both options strike me as problematic and not the only answers.
Ultimately the grounds have to be tied to each other, and you should do
that with a single solid ground plane in all but exceptional cases. In
this strategy, "splitting" the grounds amounts to knowledgable component
placement to reduce impedance coupling rather than overt division into
separate pieces, and it sounds like you already have well defined
separate digital and analog areas. I certainly would not bring the
analog and digital grounds out separately and rely entirely on external
connection to tie them together. However, after unifying the ground
plane internally I would bring out a cluster of power and ground pins for
the analog end separately from an equivalent group of pins at the digital
end. This is to keep the circulating power supply currents separated.
It should not be necessary to section the two ground types from each
other as long as you properly manage the directional flow of current.
Orin Laney
On Wed, 11 Mar 2009 11:10:14 -0700 (PDT) Jie Wang
<jie_wang_2009@xxxxxxxx> writes:
> All,
> For a 4-layer substrate package, if we assign the top layer
> as signal layer, the second and third layer would be Power and
> Ground
> planes. We have VDD/VSS and AVDD/AVSS, so we have to split the
> second
> and third layer for these two pairs of power and ground.
>
> It would have two options:
> Option 1. In second layer: two third of area as VDD, one third of
> area as AVSS,
> then in third layer: two third of area underneath of VDD is
> assigned as VSS, the rest area -AVDD.
>
> Option 2. In Second layer, two third of area as VSS, one third of
> area --AVDD,
> then third layer would be: two third of area underneath of VSS is
> assigned as VDD, the rest area --AVSS.
>
> My question is:
>
> Do both option work? Which option is better than the other?
>
>
> Thanks,
>
> Jie
>
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